3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/omap_common.h>
36 #include <asm/arch/clock.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/utils.h>
39 #include <asm/omap_gpio.h>
42 #ifndef CONFIG_SPL_BUILD
44 * printing to console doesn't work unless
45 * this code is executed from SPL
47 #define printf(fmt, args...)
51 const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */
53 20000000, /* 20 MHz */
54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */
57 27000000, /* 27 MHz */
58 38400000, /* 38.4 MHz */
61 static inline u32 __get_sys_clk_index(void)
65 * For ES1 the ROM code calibration of sys clock is not reliable
66 * due to hw issue. So, use hard-coded value. If this value is not
67 * correct for any board over-ride this function in board file
68 * From ES2.0 onwards you will get this information from
71 if (omap_revision() == OMAP4430_ES1_0)
72 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
74 /* SYS_CLKSEL - 1 to match the dpll param array indices */
75 ind = (readl((*prcm)->cm_sys_clksel) &
76 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
81 u32 get_sys_clk_index(void)
82 __attribute__ ((weak, alias("__get_sys_clk_index")));
84 u32 get_sys_clk_freq(void)
86 u8 index = get_sys_clk_index();
87 return sys_clk_array[index];
90 void setup_post_dividers(u32 const base, const struct dpll_params *params)
92 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
94 /* Setup post-dividers */
96 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
98 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
99 if (params->m4_h11 >= 0)
100 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
101 if (params->m5_h12 >= 0)
102 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
103 if (params->m6_h13 >= 0)
104 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
105 if (params->m7_h14 >= 0)
106 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
107 if (params->h21 >= 0)
108 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
109 if (params->h22 >= 0)
110 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
111 if (params->h23 >= 0)
112 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
113 if (params->h24 >= 0)
114 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
117 static inline void do_bypass_dpll(u32 const base)
119 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
121 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
122 CM_CLKMODE_DPLL_DPLL_EN_MASK,
123 DPLL_EN_FAST_RELOCK_BYPASS <<
124 CM_CLKMODE_DPLL_EN_SHIFT);
127 static inline void wait_for_bypass(u32 const base)
129 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
131 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
133 printf("Bypassing DPLL failed %x\n", base);
137 static inline void do_lock_dpll(u32 const base)
139 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
141 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
142 CM_CLKMODE_DPLL_DPLL_EN_MASK,
143 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
146 static inline void wait_for_lock(u32 const base)
148 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
150 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
151 &dpll_regs->cm_idlest_dpll, LDELAY)) {
152 printf("DPLL locking failed for %x\n", base);
157 inline u32 check_for_lock(u32 const base)
159 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
160 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
165 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
167 u32 sysclk_ind = get_sys_clk_index();
168 return &dpll_data->mpu[sysclk_ind];
171 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
173 u32 sysclk_ind = get_sys_clk_index();
174 return &dpll_data->core[sysclk_ind];
177 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
179 u32 sysclk_ind = get_sys_clk_index();
180 return &dpll_data->per[sysclk_ind];
183 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
185 u32 sysclk_ind = get_sys_clk_index();
186 return &dpll_data->iva[sysclk_ind];
189 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
191 u32 sysclk_ind = get_sys_clk_index();
192 return &dpll_data->usb[sysclk_ind];
195 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
197 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
198 u32 sysclk_ind = get_sys_clk_index();
199 return &dpll_data->abe[sysclk_ind];
201 return dpll_data->abe;
205 static const struct dpll_params *get_ddr_dpll_params
206 (struct dplls const *dpll_data)
208 u32 sysclk_ind = get_sys_clk_index();
212 return &dpll_data->ddr[sysclk_ind];
215 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
219 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
224 temp = readl(&dpll_regs->cm_clksel_dpll);
226 if (check_for_lock(base)) {
228 * The Dpll has already been locked by rom code using CH.
229 * Check if M,N are matching with Ideal nominal opp values.
230 * If matches, skip the rest otherwise relock.
232 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
233 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
234 if ((M != (params->m)) || (N != (params->n))) {
235 debug("\n %s Dpll locked, but not for ideal M = %d,"
236 "N = %d values, current values are M = %d,"
237 "N= %d" , dpll, params->m, params->n,
240 /* Dpll locked with ideal values for nominal opps. */
241 debug("\n %s Dpll already locked with ideal"
242 "nominal opp values", dpll);
243 goto setup_post_dividers;
250 temp &= ~CM_CLKSEL_DPLL_M_MASK;
251 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
253 temp &= ~CM_CLKSEL_DPLL_N_MASK;
254 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
256 writel(temp, &dpll_regs->cm_clksel_dpll);
263 setup_post_dividers(base, params);
265 /* Wait till the DPLL locks */
270 u32 omap_ddr_clk(void)
272 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
273 const struct dpll_params *core_dpll_params;
275 omap_rev = omap_revision();
276 sys_clk_khz = get_sys_clk_freq() / 1000;
278 core_dpll_params = get_core_dpll_params(*dplls_data);
280 debug("sys_clk %d\n ", sys_clk_khz * 1000);
282 /* Find Core DPLL locked frequency first */
283 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
284 (core_dpll_params->n + 1);
286 if (omap_rev < OMAP5430_ES1_0) {
288 * DDR frequency is PHY_ROOT_CLK/2
289 * PHY_ROOT_CLK = Fdpll/2/M2
294 * DDR frequency is PHY_ROOT_CLK
295 * PHY_ROOT_CLK = Fdpll/2/M2
300 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
301 ddr_clk *= 1000; /* convert to Hz */
302 debug("ddr_clk %d\n ", ddr_clk);
310 * Resulting MPU frequencies:
311 * 4430 ES1.0 : 600 MHz
312 * 4430 ES2.x : 792 MHz (OPP Turbo)
313 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
315 void configure_mpu_dpll(void)
317 const struct dpll_params *params;
318 struct dpll_regs *mpu_dpll_regs;
320 omap_rev = omap_revision();
323 * DCC and clock divider settings for 4460.
324 * DCC is required, if more than a certain frequency is required.
328 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
330 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
331 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
332 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
333 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
334 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
335 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
336 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
337 CM_CLKSEL_DCC_EN_MASK);
340 params = get_mpu_dpll_params(*dplls_data);
342 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
343 debug("MPU DPLL locked\n");
346 #ifdef CONFIG_USB_EHCI_OMAP
347 static void setup_usb_dpll(void)
349 const struct dpll_params *params;
350 u32 sys_clk_khz, sd_div, num, den;
352 sys_clk_khz = get_sys_clk_freq() / 1000;
355 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
356 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
357 * - where CLKINP is sys_clk in MHz
358 * Use CLKINP in KHz and adjust the denominator accordingly so
359 * that we have enough accuracy and at the same time no overflow
361 params = get_usb_dpll_params(*dplls_data);
362 num = params->m * sys_clk_khz;
363 den = (params->n + 1) * 250 * 1000;
366 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
367 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
368 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
370 /* Now setup the dpll with the regular function */
371 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
375 static void setup_dplls(void)
378 const struct dpll_params *params;
380 debug("setup_dplls\n");
383 params = get_core_dpll_params(*dplls_data); /* default - safest */
385 * Do not lock the core DPLL now. Just set it up.
386 * Core DPLL will be locked after setting up EMIF
387 * using the FREQ_UPDATE method(freq_update_core())
389 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
391 DPLL_NO_LOCK, "core");
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
395 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
396 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
397 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
398 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
399 writel(temp, (*prcm)->cm_clksel_core);
400 debug("Core DPLL configured\n");
403 params = get_per_dpll_params(*dplls_data);
404 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
405 params, DPLL_LOCK, "per");
406 debug("PER DPLL locked\n");
409 configure_mpu_dpll();
411 #ifdef CONFIG_USB_EHCI_OMAP
414 params = get_ddr_dpll_params(*dplls_data);
415 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
416 params, DPLL_LOCK, "ddr");
419 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
420 static void setup_non_essential_dplls(void)
423 const struct dpll_params *params;
426 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
427 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
429 params = get_iva_dpll_params(*dplls_data);
430 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
432 /* Configure ABE dpll */
433 params = get_abe_dpll_params(*dplls_data);
434 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
435 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
437 if (omap_revision() == DRA752_ES1_0)
438 /* Select the sys clk for dpll_abe */
439 clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
440 CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
441 CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
443 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
445 * We need to enable some additional options to achieve
446 * 196.608MHz from 32768 Hz
448 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
449 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
450 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
451 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
452 CM_CLKMODE_DPLL_REGM4XEN_MASK);
453 /* Spend 4 REFCLK cycles at each stage */
454 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
455 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
456 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
459 /* Select the right reference clk */
460 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
461 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
462 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
464 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
468 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
472 volt_offset -= pmic->base_offset;
474 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
477 * Offset codes 1-6 all give the base voltage in Palmas
478 * Offset code 0 switches OFF the SMPS
480 return offset_code + pmic->start_code;
483 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
486 u32 offset = volt_mv;
492 pmic->pmic_bus_init();
493 /* See if we can first get the GPIO if needed */
495 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
498 printf("%s: gpio %d request failed %d\n", __func__,
503 /* Pull the GPIO low to select SET0 register, while we program SET1 */
505 gpio_direction_output(pmic->gpio, 0);
507 /* convert to uV for better accuracy in the calculations */
510 offset_code = get_offset_code(offset, pmic);
512 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
515 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
516 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
519 gpio_direction_output(pmic->gpio, 1);
522 static u32 optimize_vcore_voltage(struct volts const *v)
530 switch (v->efuse.reg_bits) {
532 val = readw(v->efuse.reg);
535 val = readl(v->efuse.reg);
538 printf("Error: efuse 0x%08x bits=%d unknown\n",
539 v->efuse.reg, v->efuse.reg_bits);
544 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
545 v->efuse.reg, v->efuse.reg_bits, v->value);
549 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
550 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
555 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
556 * We set the maximum voltages allowed here because Smart-Reflex is not
557 * enabled in bootloader. Voltage initialization in the kernel will set
558 * these to the nominal values after enabling Smart-Reflex
560 void scale_vcores(struct vcores_data const *vcores)
564 val = optimize_vcore_voltage(&vcores->core);
565 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
567 val = optimize_vcore_voltage(&vcores->mpu);
568 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
570 /* Configure MPU ABB LDO after scale */
571 abb_setup((*ctrl)->control_std_fuse_opp_vdd_mpu_2,
572 (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl,
573 (*prcm)->prm_abbldo_mpu_setup,
574 (*prcm)->prm_abbldo_mpu_ctrl,
575 (*prcm)->prm_irqstatus_mpu_2,
576 OMAP_ABB_MPU_TXDONE_MASK,
579 val = optimize_vcore_voltage(&vcores->mm);
580 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
582 val = optimize_vcore_voltage(&vcores->gpu);
583 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
585 val = optimize_vcore_voltage(&vcores->eve);
586 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
588 val = optimize_vcore_voltage(&vcores->iva);
589 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
591 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
592 /* Configure LDO SRAM "magic" bits */
593 writel(2, (*prcm)->prm_sldo_core_setup);
594 writel(2, (*prcm)->prm_sldo_mpu_setup);
595 writel(2, (*prcm)->prm_sldo_mm_setup);
599 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
601 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
602 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
603 debug("Enable clock domain - %x\n", clkctrl_reg);
606 static inline void wait_for_clk_enable(u32 clkctrl_addr)
608 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
611 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
612 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
614 clkctrl = readl(clkctrl_addr);
615 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
616 MODULE_CLKCTRL_IDLEST_SHIFT;
618 printf("Clock enable failed for 0x%x idlest 0x%x\n",
619 clkctrl_addr, clkctrl);
625 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
628 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
629 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
630 debug("Enable clock module - %x\n", clkctrl_addr);
632 wait_for_clk_enable(clkctrl_addr);
635 void freq_update_core(void)
637 u32 freq_config1 = 0;
638 const struct dpll_params *core_dpll_params;
639 u32 omap_rev = omap_revision();
641 core_dpll_params = get_core_dpll_params(*dplls_data);
642 /* Put EMIF clock domain in sw wakeup mode */
643 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
644 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
645 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
646 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
648 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
649 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
651 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
652 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
654 freq_config1 |= (core_dpll_params->m2 <<
655 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
656 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
658 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
659 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
660 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
661 puts("FREQ UPDATE procedure failed!!");
666 * Putting EMIF in HW_AUTO is seen to be causing issues with
667 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
668 * in OMAP5430 ES1.0 silicon
670 if (omap_rev != OMAP5430_ES1_0) {
671 /* Put EMIF clock domain back in hw auto mode */
672 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
673 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
674 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
675 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
679 void bypass_dpll(u32 const base)
681 do_bypass_dpll(base);
682 wait_for_bypass(base);
685 void lock_dpll(u32 const base)
691 void setup_clocks_for_console(void)
693 /* Do not add any spl_debug prints in this function */
694 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
695 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
696 CD_CLKCTRL_CLKTRCTRL_SHIFT);
698 /* Enable all UARTs - console will be on one of them */
699 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
700 MODULE_CLKCTRL_MODULEMODE_MASK,
701 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
702 MODULE_CLKCTRL_MODULEMODE_SHIFT);
704 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
705 MODULE_CLKCTRL_MODULEMODE_MASK,
706 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
707 MODULE_CLKCTRL_MODULEMODE_SHIFT);
709 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
710 MODULE_CLKCTRL_MODULEMODE_MASK,
711 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
712 MODULE_CLKCTRL_MODULEMODE_SHIFT);
714 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
715 MODULE_CLKCTRL_MODULEMODE_MASK,
716 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
717 MODULE_CLKCTRL_MODULEMODE_SHIFT);
719 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
720 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
721 CD_CLKCTRL_CLKTRCTRL_SHIFT);
724 void do_enable_clocks(u32 const *clk_domains,
725 u32 const *clk_modules_hw_auto,
726 u32 const *clk_modules_explicit_en,
731 /* Put the clock domains in SW_WKUP mode */
732 for (i = 0; (i < max) && clk_domains[i]; i++) {
733 enable_clock_domain(clk_domains[i],
734 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
737 /* Clock modules that need to be put in HW_AUTO */
738 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
739 enable_clock_module(clk_modules_hw_auto[i],
740 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
744 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
745 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
746 enable_clock_module(clk_modules_explicit_en[i],
747 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
751 /* Put the clock domains in HW_AUTO mode now */
752 for (i = 0; (i < max) && clk_domains[i]; i++) {
753 enable_clock_domain(clk_domains[i],
754 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
760 switch (omap_hw_init_context()) {
761 case OMAP_INIT_CONTEXT_SPL:
762 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
763 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
764 enable_basic_clocks();
766 scale_vcores(*omap_vcores);
768 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
769 setup_non_essential_dplls();
770 enable_non_essential_clocks();
772 setup_warmreset_time();
778 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
779 enable_basic_uboot_clocks();
782 void gpi2c_init(void)
784 static int gpi2c = 1;
787 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);