3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/cache.h>
27 #include <asm/armv7.h>
29 #include <asm/omap_common.h>
30 #include <asm/arch/mmc_host_def.h>
32 #include <linux/compiler.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 extern omap3_sysinfo sysinfo;
38 static void omap3_setup_aux_cr(void);
39 #ifndef CONFIG_SYS_L2CACHE_OFF
40 static void omap3_invalidate_l2_cache_secure(void);
44 static const struct omap_gpio_platdata omap34xx_gpio[] = {
45 { 0, OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
46 { 1, OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
47 { 2, OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
48 { 3, OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
49 { 4, OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
50 { 5, OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
53 U_BOOT_DEVICES(am33xx_gpios) = {
54 { "gpio_omap", &omap34xx_gpio[0] },
55 { "gpio_omap", &omap34xx_gpio[1] },
56 { "gpio_omap", &omap34xx_gpio[2] },
57 { "gpio_omap", &omap34xx_gpio[3] },
58 { "gpio_omap", &omap34xx_gpio[4] },
59 { "gpio_omap", &omap34xx_gpio[5] },
64 static const struct gpio_bank gpio_bank_34xx[6] = {
65 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
66 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
67 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
68 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
69 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
70 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
73 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
77 #ifdef CONFIG_SPL_BUILD
79 * We use static variables because global data is not ready yet.
80 * Initialized data is available in SPL right from the beginning.
81 * We would not typically need to save these parameters in regular
82 * U-Boot. This is needed only in SPL at the moment.
84 u32 omap3_boot_device = BOOT_DEVICE_NAND;
86 /* auto boot mode detection is not possible for OMAP3 - hard code */
87 u32 spl_boot_mode(void)
89 switch (spl_boot_device()) {
90 case BOOT_DEVICE_MMC2:
91 return MMCSD_MODE_RAW;
92 case BOOT_DEVICE_MMC1:
93 return MMCSD_MODE_FAT;
96 puts("spl: ERROR: unknown device - can't select boot mode\n");
101 u32 spl_boot_device(void)
103 return omap3_boot_device;
106 int board_mmc_init(bd_t *bis)
108 switch (spl_boot_device()) {
109 case BOOT_DEVICE_MMC1:
110 omap_mmc_init(0, 0, 0, -1, -1);
112 case BOOT_DEVICE_MMC2:
113 case BOOT_DEVICE_MMC2_2:
114 omap_mmc_init(1, 0, 0, -1, -1);
120 void spl_board_init(void)
122 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
125 #ifdef CONFIG_SPL_I2C_SUPPORT
126 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
129 #endif /* CONFIG_SPL_BUILD */
132 /******************************************************************************
133 * Routine: secure_unlock
134 * Description: Setup security registers for access
136 *****************************************************************************/
137 void secure_unlock_mem(void)
139 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
140 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
141 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
142 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
143 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
145 /* Protection Module Register Target APE (PM_RT) */
146 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
147 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
148 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
149 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
151 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
152 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
153 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
155 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
156 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
157 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
158 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
161 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
162 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
163 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
165 /* SDRC region 0 public */
166 writel(UNLOCK_1, &sms_base->rg_att0);
169 /******************************************************************************
170 * Routine: secureworld_exit()
171 * Description: If chip is EMU and boot type is external
172 * configure secure registers and exit secure world
174 *****************************************************************************/
175 void secureworld_exit(void)
179 /* configure non-secure access control register */
180 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
181 /* enabling co-processor CP10 and CP11 accesses in NS world */
182 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
184 * allow allocation of locked TLBs and L2 lines in NS world
185 * allow use of PLE registers in NS world also
187 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
188 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
190 /* Enable ASA in ACR register */
191 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
192 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
193 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
195 /* Exiting secure world */
196 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
197 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
198 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
201 /******************************************************************************
202 * Routine: try_unlock_sram()
203 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
205 *****************************************************************************/
206 void try_unlock_memory(void)
209 int in_sdram = is_running_in_sdram();
212 * if GP device unlock device SRAM for general use
213 * secure code breaks for Secure/Emulation device - HS/E/T
215 mode = get_device_type();
216 if (mode == GP_DEVICE)
220 * If device is EMU and boot is XIP external booting
221 * Unlock firewalls and disable L2 and put chip
222 * out of secure world
224 * Assuming memories are unlocked by the demon who put us in SDRAM
226 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
235 /******************************************************************************
237 * Description: Does early system init of muxing and clocks.
238 * - Called path is with SRAM stack.
239 *****************************************************************************/
242 int in_sdram = is_running_in_sdram();
248 /* Errata workarounds */
249 omap3_setup_aux_cr();
251 #ifndef CONFIG_SYS_L2CACHE_OFF
252 /* Invalidate L2-cache from secure mode */
253 omap3_invalidate_l2_cache_secure();
263 #ifdef CONFIG_USB_EHCI_OMAP
264 ehci_clocks_enable();
267 #ifdef CONFIG_SPL_BUILD
270 preloader_console_init();
280 * Routine: misc_init_r
281 * Description: A basic misc_init_r that just displays the die ID
283 int __weak misc_init_r(void)
290 /******************************************************************************
291 * Routine: wait_for_command_complete
292 * Description: Wait for posting to finish on watchdog
293 *****************************************************************************/
294 static void wait_for_command_complete(struct watchdog *wd_base)
298 pending = readl(&wd_base->wwps);
302 /******************************************************************************
303 * Routine: watchdog_init
304 * Description: Shut down watch dogs
305 *****************************************************************************/
306 void watchdog_init(void)
308 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
309 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
312 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
313 * either taken care of by ROM (HS/EMU) or not accessible (GP).
314 * We need to take care of WD2-MPU or take a PRCM reset. WD3
315 * should not be running and does not generate a PRCM reset.
318 setbits_le32(&prcm_base->fclken_wkup, 0x20);
319 setbits_le32(&prcm_base->iclken_wkup, 0x20);
320 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
322 writel(WD_UNLOCK1, &wd2_base->wspr);
323 wait_for_command_complete(wd2_base);
324 writel(WD_UNLOCK2, &wd2_base->wspr);
327 /******************************************************************************
328 * Dummy function to handle errors for EABI incompatibility
329 *****************************************************************************/
334 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
335 /******************************************************************************
336 * OMAP3 specific command to switch between NAND HW and SW ecc
337 *****************************************************************************/
338 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
340 if (argc < 2 || argc > 3)
343 if (strncmp(argv[1], "hw", 2) == 0) {
345 omap_nand_switch_ecc(1, 1);
347 if (strncmp(argv[2], "hamming", 7) == 0)
348 omap_nand_switch_ecc(1, 1);
349 else if (strncmp(argv[2], "bch8", 4) == 0)
350 omap_nand_switch_ecc(1, 8);
354 } else if (strncmp(argv[1], "sw", 2) == 0) {
355 omap_nand_switch_ecc(0, 0);
363 printf ("Usage: nandecc %s\n", cmdtp->usage);
368 nandecc, 3, 1, do_switch_ecc,
369 "switch OMAP3 NAND ECC calculation algorithm",
370 "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
372 " ecc calculation (second parameter may"
374 "nandecc sw - Switch to NAND software ecc algorithm."
377 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
379 #ifdef CONFIG_DISPLAY_BOARDINFO
381 * Print board information
383 int checkboard (void)
392 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
393 sysinfo.nand_string);
397 #endif /* CONFIG_DISPLAY_BOARDINFO */
399 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
401 u32 i, num_params = *parameters;
402 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
405 * copy the parameters to an un-cached area to avoid coherency
408 for (i = 0; i < num_params; i++) {
409 __raw_writel(*parameters, sram_scratch_space);
411 sram_scratch_space++;
414 /* Now make the PPA call */
415 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
418 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
423 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
427 if (get_device_type() == GP_DEVICE) {
428 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
431 struct emu_hal_params emu_romcode_params;
432 emu_romcode_params.num_params = 1;
433 emu_romcode_params.param1 = acr;
434 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
435 (u32 *)&emu_romcode_params);
439 static void omap3_setup_aux_cr(void)
441 /* Workaround for Cortex-A8 errata: #454179 #430973
443 * Set "Disable Branch Size Mispredicts" bit
444 * Workaround for erratum #621766
446 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
448 omap3_update_aux_cr_secure(0xE0, 0);
451 #ifndef CONFIG_SYS_L2CACHE_OFF
452 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
457 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
461 /* Write ACR - affects non-secure banked bits */
462 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
465 /* Invalidate the entire L2 cache from secure mode */
466 static void omap3_invalidate_l2_cache_secure(void)
468 if (get_device_type() == GP_DEVICE) {
469 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
472 struct emu_hal_params emu_romcode_params;
473 emu_romcode_params.num_params = 1;
474 emu_romcode_params.param1 = 0;
475 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
476 (u32 *)&emu_romcode_params);
480 void v7_outer_cache_enable(void)
483 omap3_update_aux_cr_secure(0x2, 0);
486 * On some revisions L2EN bit is banked on some revisions it's not
487 * No harm in setting both banked bits(in fact this is required
490 omap3_update_aux_cr(0x2, 0);
493 void omap3_outer_cache_disable(void)
496 omap3_update_aux_cr_secure(0, 0x2);
499 * On some revisions L2EN bit is banked on some revisions it's not
500 * No harm in clearing both banked bits(in fact this is required
503 omap3_update_aux_cr(0, 0x2);
505 #endif /* !CONFIG_SYS_L2CACHE_OFF */