3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/mem.h>
25 #include <asm/cache.h>
26 #include <asm/armv7.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/omap_common.h>
29 #include <asm/arch/mmc_host_def.h>
31 #include <linux/compiler.h>
33 DECLARE_GLOBAL_DATA_PTR;
36 extern omap3_sysinfo sysinfo;
37 static void omap3_setup_aux_cr(void);
38 #ifndef CONFIG_SYS_L2CACHE_OFF
39 static void omap3_invalidate_l2_cache_secure(void);
42 static const struct gpio_bank gpio_bank_34xx[6] = {
43 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
44 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
45 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
46 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
51 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
53 #ifdef CONFIG_SPL_BUILD
55 * We use static variables because global data is not ready yet.
56 * Initialized data is available in SPL right from the beginning.
57 * We would not typically need to save these parameters in regular
58 * U-Boot. This is needed only in SPL at the moment.
60 u32 omap3_boot_device = BOOT_DEVICE_NAND;
62 /* auto boot mode detection is not possible for OMAP3 - hard code */
63 u32 spl_boot_mode(void)
65 switch (spl_boot_device()) {
66 case BOOT_DEVICE_MMC2:
67 return MMCSD_MODE_RAW;
68 case BOOT_DEVICE_MMC1:
69 return MMCSD_MODE_FAT;
72 puts("spl: ERROR: unknown device - can't select boot mode\n");
77 u32 spl_boot_device(void)
79 return omap3_boot_device;
82 int board_mmc_init(bd_t *bis)
84 switch (spl_boot_device()) {
85 case BOOT_DEVICE_MMC1:
86 omap_mmc_init(0, 0, 0, -1, -1);
88 case BOOT_DEVICE_MMC2:
89 case BOOT_DEVICE_MMC2_2:
90 omap_mmc_init(1, 0, 0, -1, -1);
96 void spl_board_init(void)
98 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
101 #ifdef CONFIG_SPL_I2C_SUPPORT
102 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
105 #endif /* CONFIG_SPL_BUILD */
108 /******************************************************************************
109 * Routine: secure_unlock
110 * Description: Setup security registers for access
112 *****************************************************************************/
113 void secure_unlock_mem(void)
115 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
116 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
117 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
118 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
119 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
121 /* Protection Module Register Target APE (PM_RT) */
122 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
123 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
124 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
125 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
127 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
128 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
129 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
131 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
132 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
133 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
134 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
137 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
138 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
139 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
141 /* SDRC region 0 public */
142 writel(UNLOCK_1, &sms_base->rg_att0);
145 /******************************************************************************
146 * Routine: secureworld_exit()
147 * Description: If chip is EMU and boot type is external
148 * configure secure registers and exit secure world
150 *****************************************************************************/
151 void secureworld_exit(void)
155 /* configure non-secure access control register */
156 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
157 /* enabling co-processor CP10 and CP11 accesses in NS world */
158 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
160 * allow allocation of locked TLBs and L2 lines in NS world
161 * allow use of PLE registers in NS world also
163 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
164 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
166 /* Enable ASA in ACR register */
167 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
168 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
169 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
171 /* Exiting secure world */
172 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
173 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
174 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
177 /******************************************************************************
178 * Routine: try_unlock_sram()
179 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
181 *****************************************************************************/
182 void try_unlock_memory(void)
185 int in_sdram = is_running_in_sdram();
188 * if GP device unlock device SRAM for general use
189 * secure code breaks for Secure/Emulation device - HS/E/T
191 mode = get_device_type();
192 if (mode == GP_DEVICE)
196 * If device is EMU and boot is XIP external booting
197 * Unlock firewalls and disable L2 and put chip
198 * out of secure world
200 * Assuming memories are unlocked by the demon who put us in SDRAM
202 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
211 /******************************************************************************
213 * Description: Does early system init of muxing and clocks.
214 * - Called path is with SRAM stack.
215 *****************************************************************************/
218 int in_sdram = is_running_in_sdram();
224 /* Errata workarounds */
225 omap3_setup_aux_cr();
227 #ifndef CONFIG_SYS_L2CACHE_OFF
228 /* Invalidate L2-cache from secure mode */
229 omap3_invalidate_l2_cache_secure();
239 #ifdef CONFIG_USB_EHCI_OMAP
240 ehci_clocks_enable();
243 #ifdef CONFIG_SPL_BUILD
246 preloader_console_init();
256 * Routine: misc_init_r
257 * Description: A basic misc_init_r that just displays the die ID
259 int __weak misc_init_r(void)
266 /******************************************************************************
267 * Routine: wait_for_command_complete
268 * Description: Wait for posting to finish on watchdog
269 *****************************************************************************/
270 static void wait_for_command_complete(struct watchdog *wd_base)
274 pending = readl(&wd_base->wwps);
278 /******************************************************************************
279 * Routine: watchdog_init
280 * Description: Shut down watch dogs
281 *****************************************************************************/
282 void watchdog_init(void)
284 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
285 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
288 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
289 * either taken care of by ROM (HS/EMU) or not accessible (GP).
290 * We need to take care of WD2-MPU or take a PRCM reset. WD3
291 * should not be running and does not generate a PRCM reset.
294 setbits_le32(&prcm_base->fclken_wkup, 0x20);
295 setbits_le32(&prcm_base->iclken_wkup, 0x20);
296 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
298 writel(WD_UNLOCK1, &wd2_base->wspr);
299 wait_for_command_complete(wd2_base);
300 writel(WD_UNLOCK2, &wd2_base->wspr);
303 /******************************************************************************
304 * Dummy function to handle errors for EABI incompatibility
305 *****************************************************************************/
310 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
311 /******************************************************************************
312 * OMAP3 specific command to switch between NAND HW and SW ecc
313 *****************************************************************************/
314 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
316 if (argc < 2 || argc > 3)
319 if (strncmp(argv[1], "hw", 2) == 0) {
321 omap_nand_switch_ecc(1, 1);
323 if (strncmp(argv[2], "hamming", 7) == 0)
324 omap_nand_switch_ecc(1, 1);
325 else if (strncmp(argv[2], "bch8", 4) == 0)
326 omap_nand_switch_ecc(1, 8);
330 } else if (strncmp(argv[1], "sw", 2) == 0) {
331 omap_nand_switch_ecc(0, 0);
339 printf ("Usage: nandecc %s\n", cmdtp->usage);
344 nandecc, 3, 1, do_switch_ecc,
345 "switch OMAP3 NAND ECC calculation algorithm",
346 "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and"
348 " ecc calculation (second parameter may"
350 "nandecc sw - Switch to NAND software ecc algorithm."
353 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
355 #ifdef CONFIG_DISPLAY_BOARDINFO
357 * Print board information
359 int checkboard (void)
368 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
369 sysinfo.nand_string);
373 #endif /* CONFIG_DISPLAY_BOARDINFO */
375 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
377 u32 i, num_params = *parameters;
378 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
381 * copy the parameters to an un-cached area to avoid coherency
384 for (i = 0; i < num_params; i++) {
385 __raw_writel(*parameters, sram_scratch_space);
387 sram_scratch_space++;
390 /* Now make the PPA call */
391 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
394 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
399 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
403 if (get_device_type() == GP_DEVICE) {
404 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
407 struct emu_hal_params emu_romcode_params;
408 emu_romcode_params.num_params = 1;
409 emu_romcode_params.param1 = acr;
410 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
411 (u32 *)&emu_romcode_params);
415 static void omap3_setup_aux_cr(void)
417 /* Workaround for Cortex-A8 errata: #454179 #430973
419 * Set "Disable Branch Size Mispredicts" bit
420 * Workaround for erratum #621766
422 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
424 omap3_update_aux_cr_secure(0xE0, 0);
427 #ifndef CONFIG_SYS_L2CACHE_OFF
428 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
433 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
437 /* Write ACR - affects non-secure banked bits */
438 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
441 /* Invalidate the entire L2 cache from secure mode */
442 static void omap3_invalidate_l2_cache_secure(void)
444 if (get_device_type() == GP_DEVICE) {
445 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
448 struct emu_hal_params emu_romcode_params;
449 emu_romcode_params.num_params = 1;
450 emu_romcode_params.param1 = 0;
451 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
452 (u32 *)&emu_romcode_params);
456 void v7_outer_cache_enable(void)
459 omap3_update_aux_cr_secure(0x2, 0);
462 * On some revisions L2EN bit is banked on some revisions it's not
463 * No harm in setting both banked bits(in fact this is required
466 omap3_update_aux_cr(0x2, 0);
469 void omap3_outer_cache_disable(void)
472 omap3_update_aux_cr_secure(0, 0x2);
475 * On some revisions L2EN bit is banked on some revisions it's not
476 * No harm in clearing both banked bits(in fact this is required
479 omap3_update_aux_cr(0, 0x2);
481 #endif /* !CONFIG_SYS_L2CACHE_OFF */