2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mem.h>
33 #include <asm/arch/clocks_omap3.h>
36 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
38 .global save_boot_params
40 #warning "Please implement save_boot_params for OMAP3"
43 .global omap3_gp_romcode_call
44 omap3_gp_romcode_call:
45 PUSH {r4-r12, lr} @ Save all registers from ROM code!
46 MOV r12, r0 @ Copy the Service ID in R12
47 MOV r0, r1 @ Copy parameter to R0
48 mcr p15, 0, r0, c7, c10, 4 @ DSB
49 mcr p15, 0, r0, c7, c10, 5 @ DMB
50 .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
51 @ because we use -march=armv5
55 * Funtion for making PPA HAL API calls in secure devices
60 .global do_omap3_emu_romcode_call
61 do_omap3_emu_romcode_call:
62 PUSH {r4-r12, lr} @ Save all registers from ROM code!
63 MOV r12, r0 @ Copy the Secure Service ID in R12
64 MOV r3, r1 @ Copy the pointer to va_list in R3
65 MOV r1, #0 @ Process ID - 0
66 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
68 MOV r6, #0xFF @ Indicate new Task call
69 mcr p15, 0, r0, c7, c10, 4 @ DSB
70 mcr p15, 0, r0, c7, c10, 5 @ DMB
71 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
72 @ because we use -march=armv5
75 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
76 /**************************************************************************
77 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
78 * R1 = SRAM destination address.
79 *************************************************************************/
82 /* Copy DPLL code into SRAM */
83 adr r0, go_to_speed /* get addr of clock setting code */
84 mov r2, #384 /* r2 size to copy (div by 32 bytes) */
85 mov r1, r1 /* r1 <- dest address (passed in) */
86 add r2, r2, r0 /* r2 <- source end address */
88 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
89 stmia r1!, {r3 - r10} /* copy to target address [r1] */
90 cmp r0, r2 /* until source end address [r2] */
92 mov pc, lr /* back to caller */
94 /* ***************************************************************************
95 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
96 * -executed from SRAM.
97 * R0 = CM_CLKEN_PLL-bypass value
98 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
99 * R2 = CM_CLKSEL_CORE-divider values
100 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
102 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
103 * confused. A reset of the controller gets it back. Taking away its
104 * L3 when its not in self refresh seems bad for it. Normally, this
105 * code runs from flash before SDR is init so that should be ok.
106 ****************************************************************************/
111 /* move into fast relock bypass */
115 ldr r5, [r3] /* get status */
116 and r5, r5, #0x1 /* isolate core status */
117 cmp r5, #0x1 /* still locked? */
118 beq wait1 /* if lock, loop */
120 /* set new dpll dividers _after_ in bypass */
122 str r1, [r5] /* set m, n, m2 */
124 str r2, [r5] /* set l3/l4/.. dividers*/
125 ldr r5, pll_div_add3 /* wkup */
126 ldr r2, pll_div_val3 /* rsm val */
128 ldr r5, pll_div_add4 /* gfx */
131 ldr r5, pll_div_add5 /* emu */
135 /* now prepare GPMC (flash) for new dpll speed */
136 /* flash needs to be stable when we jump back to it */
137 ldr r5, flash_cfg3_addr
138 ldr r2, flash_cfg3_val
140 ldr r5, flash_cfg4_addr
141 ldr r2, flash_cfg4_val
143 ldr r5, flash_cfg5_addr
144 ldr r2, flash_cfg5_val
146 ldr r5, flash_cfg1_addr
148 orr r2, r2, #0x3 /* up gpmc divider */
151 /* lock DPLL3 and wait a bit */
152 orr r0, r0, #0x7 /* set up for lock mode */
153 str r0, [r4] /* lock */
154 nop /* ARM slow at this point working at sys_clk */
159 ldr r5, [r3] /* get status */
160 and r5, r5, #0x1 /* isolate core status */
161 cmp r5, #0x1 /* still locked? */
162 bne wait2 /* if lock, loop */
168 mov pc, lr /* back to caller, locked */
170 _go_to_speed: .word go_to_speed
172 /* these constants need to be close for PIC code */
173 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
175 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
177 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
179 .word STNOR_GPMC_CONFIG3
181 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
183 .word STNOR_GPMC_CONFIG4
185 .word STNOR_GPMC_CONFIG5
187 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
197 .word (WKUP_RSM << 1)
212 str ip, [sp] /* stash old link register */
213 mov ip, lr /* save link reg across call */
214 bl s_init /* go setup pll, mux, memory */
215 ldr ip, [sp] /* restore save ip */
216 mov lr, ip /* restore link reg */
218 /* back to arch calling code */
221 /* the literal pools origin */
227 .word LOW_LEVEL_SRAM_STACK
229 /* DPLL(1-4) PARAM TABLES */
232 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
233 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
234 * The values are defined for all possible sysclk and for ES1 and ES2.
240 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
242 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
244 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
248 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
250 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
252 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
256 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
258 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
260 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
264 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
266 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
268 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
272 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
274 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
276 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
279 .globl get_mpu_dpll_param
281 adr r0, mpu_dpll_param
287 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
289 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
291 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
295 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
297 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
299 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
303 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
305 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
307 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
311 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
313 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
315 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
319 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
321 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
323 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
326 .globl get_iva_dpll_param
328 adr r0, iva_dpll_param
331 /* Core DPLL targets for L3 at 166 & L133 */
335 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
337 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
339 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
343 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
345 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
347 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
351 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
353 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
355 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
359 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
361 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
363 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
367 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
369 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
371 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
373 .globl get_core_dpll_param
375 adr r0, core_dpll_param
378 /* PER DPLL values are same for both ES1 and ES2 */
381 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
384 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
387 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
390 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
393 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
395 .globl get_per_dpll_param
397 adr r0, per_dpll_param
400 /* PER2 DPLL values */
403 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
406 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
409 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
412 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
415 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
417 .globl get_per2_dpll_param
419 adr r0, per2_dpll_param
423 * Tables for 36XX/37XX devices
463 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
464 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
465 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
466 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
467 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
468 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
470 .globl get_36x_mpu_dpll_param
471 get_36x_mpu_dpll_param:
472 adr r0, mpu_36x_dpll_param
475 .globl get_36x_iva_dpll_param
476 get_36x_iva_dpll_param:
477 adr r0, iva_36x_dpll_param
480 .globl get_36x_core_dpll_param
481 get_36x_core_dpll_param:
482 adr r0, core_36x_dpll_param
485 .globl get_36x_per_dpll_param
486 get_36x_per_dpll_param:
487 adr r0, per_36x_dpll_param