2 * Timing and Organization details of the Elpida parts used in OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/sys_proto.h>
17 * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
18 * SDP and Panda. Since the parts used and geometry are identical for
19 * SDP and Panda for a given OMAP4 revision, this information is kept
20 * here instead of being in board directory. However the key functions
21 * exported are weakly linked so that they can be over-ridden in the board
22 * directory if there is a OMAP4 board in the future that uses a different
23 * memory device or geometry.
25 * For any new board with different memory devices over-ride one or more
26 * of the following functions as per the CONFIG flags you intend to enable:
27 * - emif_get_reg_dump()
28 * - emif_get_dmm_regs()
29 * - emif_get_device_details()
30 * - emif_get_device_timings()
33 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
35 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
36 .sdram_config_init = 0x80000eb9,
37 .sdram_config = 0x80001ab9,
38 .ref_ctrl = 0x0000030c,
39 .sdram_tim1 = 0x08648311,
40 .sdram_tim2 = 0x101b06ca,
41 .sdram_tim3 = 0x0048a19f,
42 .read_idle_ctrl = 0x000501ff,
43 .zq_config = 0x500b3214,
44 .temp_alert_config = 0xd8016893,
45 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
46 .emif_ddr_phy_ctlr_1 = 0x049ff808
49 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
50 .sdram_config_init = 0x80000eb1,
51 .sdram_config = 0x80001ab1,
52 .ref_ctrl = 0x000005cd,
53 .sdram_tim1 = 0x10cb0622,
54 .sdram_tim2 = 0x20350d52,
55 .sdram_tim3 = 0x00b1431f,
56 .read_idle_ctrl = 0x000501ff,
57 .zq_config = 0x500b3214,
58 .temp_alert_config = 0x58016893,
59 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
60 .emif_ddr_phy_ctlr_1 = 0x049ff418
63 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
64 .sdram_config_init = 0x80000eb9,
65 .sdram_config = 0x80001ab9,
66 .ref_ctrl = 0x00000618,
67 .sdram_tim1 = 0x10eb0662,
68 .sdram_tim2 = 0x20370dd2,
69 .sdram_tim3 = 0x00b1c33f,
70 .read_idle_ctrl = 0x000501ff,
71 .zq_config = 0xd00b3214,
72 .temp_alert_config = 0xd8016893,
73 .emif_ddr_phy_ctlr_1_init = 0x049ffff5,
74 .emif_ddr_phy_ctlr_1 = 0x049ff418
77 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
78 .dmm_lisa_map_0 = 0xFF020100,
81 .dmm_lisa_map_3 = 0x80540300,
85 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
86 .dmm_lisa_map_0 = 0xFF020100,
89 .dmm_lisa_map_3 = 0x80640300,
93 const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
94 .dmm_lisa_map_0 = 0xFF020100,
97 .dmm_lisa_map_3 = 0x80640300,
101 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
103 u32 omap4_rev = omap_revision();
105 /* Same devices and geometry on both EMIFs */
106 if (omap4_rev == OMAP4430_ES1_0)
107 *regs = &emif_regs_elpida_380_mhz_1cs;
108 else if (omap4_rev == OMAP4430_ES2_0)
109 *regs = &emif_regs_elpida_200_mhz_2cs;
111 *regs = &emif_regs_elpida_400_mhz_2cs;
113 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
114 __attribute__((weak, alias("emif_get_reg_dump_sdp")));
116 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
119 u32 omap_rev = omap_revision();
121 if (omap_rev == OMAP4430_ES1_0)
122 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
123 else if (omap_rev < OMAP4460_ES1_0)
124 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
126 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
129 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
130 __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
134 static const struct lpddr2_device_details elpida_2G_S4_details = {
135 .type = LPDDR2_TYPE_S4,
136 .density = LPDDR2_DENSITY_2Gb,
137 .io_width = LPDDR2_IO_WIDTH_32,
138 .manufacturer = LPDDR2_MANUFACTURER_ELPIDA
141 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
142 struct lpddr2_device_details *lpddr2_dev_details)
144 u32 omap_rev = omap_revision();
146 /* EMIF1 & EMIF2 have identical configuration */
147 if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
148 /* Nothing connected on CS1 for ES1.0 */
151 /* In all other cases Elpida 2G device */
152 *lpddr2_dev_details = elpida_2G_S4_details;
153 return lpddr2_dev_details;
157 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
158 struct lpddr2_device_details *lpddr2_dev_details)
159 __attribute__((weak, alias("emif_get_device_details_sdp")));
161 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
163 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
164 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
165 .max_freq = 400000000,
187 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
188 .max_freq = 333000000,
210 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
211 .max_freq = 200000000,
233 static const struct lpddr2_min_tck min_tck_elpida = {
248 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
249 &timings_elpida_200_mhz,
250 &timings_elpida_333_mhz,
251 &timings_elpida_400_mhz
254 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
255 .ac_timings = elpida_ac_timings,
256 .min_tck = &min_tck_elpida,
259 void emif_get_device_timings_sdp(u32 emif_nr,
260 const struct lpddr2_device_timings **cs0_device_timings,
261 const struct lpddr2_device_timings **cs1_device_timings)
263 u32 omap_rev = omap_revision();
265 /* Identical devices on EMIF1 & EMIF2 */
266 *cs0_device_timings = &elpida_2G_S4_timings;
268 if (omap_rev == OMAP4430_ES1_0)
269 *cs1_device_timings = NULL;
271 *cs1_device_timings = &elpida_2G_S4_timings;
274 void emif_get_device_timings(u32 emif_nr,
275 const struct lpddr2_device_timings **cs0_device_timings,
276 const struct lpddr2_device_timings **cs1_device_timings)
277 __attribute__((weak, alias("emif_get_device_timings_sdp")));
279 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
281 const struct lpddr2_mr_regs mr_regs = {
282 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
285 .mr10 = MR10_ZQ_ZQINIT,
286 .mr16 = MR16_REF_FULL_ARRAY
289 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)