arch/arm/cpu/armv7/socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <altera.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <asm/arch/system_manager.h>
  14 #include <asm/arch/dwmmc.h>
  15 #include <asm/arch/nic301.h>
  16 #include <asm/arch/scu.h>
  17 #include <asm/pl310.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static struct pl310_regs *const pl310 =
  22         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  23 static struct socfpga_system_manager *sysmgr_regs =
  24         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  25 static struct nic301_registers *nic301_regs =
  26         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  27 static struct scu_registers *scu_regs =
  28         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  29
  30 int dram_init(void)
  31 {
  32         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  33         return 0;
  34 }
  35
  36 /*
  37  * DesignWare Ethernet initialization
  38  */
  39 #ifdef CONFIG_DESIGNWARE_ETH
  40 int cpu_eth_init(bd_t *bis)
  41 {
  42 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  43         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  44 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  45         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  46 #else
  47 #error "Incorrect CONFIG_EMAC_BASE value!"
  48 #endif
  49
  50         /* Initialize EMAC. This needs to be done at least once per boot. */
  51
  52         /*
  53          * Putting the EMAC controller to reset when configuring the PHY
  54          * interface select at System Manager
  55          */
  56         socfpga_emac_reset(1);
  57
  58         /* Clearing emac0 PHY interface select to 0 */
  59         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  60                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  61
  62         /* configure to PHY interface select choosed */
  63         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  64                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  65
  66         /* Release the EMAC controller from reset */
  67         socfpga_emac_reset(0);
  68
  69         /* initialize and register the emac */
  70         return designware_initialize(CONFIG_EMAC_BASE,
  71                                      CONFIG_PHY_INTERFACE_MODE);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_DWMMC
  76 /*
  77  * Initializes MMC controllers.
  78  * to override, implement board_mmc_init()
  79  */
  80 int cpu_mmc_init(bd_t *bis)
  81 {
  82         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  83                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
  84 }
  85 #endif
  86
  87 #if defined(CONFIG_DISPLAY_CPUINFO)
  88 /*
  89  * Print CPU information
  90  */
  91 int print_cpuinfo(void)
  92 {
  93         puts("CPU:   Altera SoCFPGA Platform\n");
  94         return 0;
  95 }
  96 #endif
  97
  98 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  99 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 100 int overwrite_console(void)
 101 {
 102         return 0;
 103 }
 104 #endif
 105
 106 #ifdef CONFIG_FPGA
 107 /*
 108  * FPGA programming support for SoC FPGA Cyclone V
 109  */
 110 static Altera_desc altera_fpga[] = {
 111         {
 112                 /* Family */
 113                 Altera_SoCFPGA,
 114                 /* Interface type */
 115                 fast_passive_parallel,
 116                 /* No limitation as additional data will be ignored */
 117                 -1,
 118                 /* No device function table */
 119                 NULL,
 120                 /* Base interface address specified in driver */
 121                 NULL,
 122                 /* No cookie implementation */
 123                 0
 124         },
 125 };
 126
 127 /* add device descriptor to FPGA device table */
 128 static void socfpga_fpga_add(void)
 129 {
 130         int i;
 131         fpga_init();
 132         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 133                 fpga_add(fpga_altera, &altera_fpga[i]);
 134 }
 135 #else
 136 static inline void socfpga_fpga_add(void) {}
 137 #endif
 138
 139 int arch_cpu_init(void)
 140 {
 141         /*
 142          * If the HW watchdog is NOT enabled, make sure it is not running,
 143          * for example because it was enabled in the preloader. This might
 144          * trigger a watchdog-triggered reboot of Linux kernel later.
 145          */
 146 #ifndef CONFIG_HW_WATCHDOG
 147         socfpga_watchdog_reset();
 148 #endif
 149         return 0;
 150 }
 151
 152 /*
 153  * Convert all NIC-301 AMBA slaves from secure to non-secure
 154  */
 155 static void socfpga_nic301_slave_ns(void)
 156 {
 157         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 158         writel(0x1, &nic301_regs->hps2fpgaregs);
 159         writel(0x1, &nic301_regs->acp);
 160         writel(0x1, &nic301_regs->rom);
 161         writel(0x1, &nic301_regs->ocram);
 162         writel(0x1, &nic301_regs->sdrdata);
 163 }
 164
 165 int misc_init_r(void)
 166 {
 167         socfpga_bridges_reset(1);
 168         socfpga_nic301_slave_ns();
 169
 170         /*
 171          * Private components security:
 172          * U-Boot : configure private timer, global timer and cpu component
 173          * access as non secure for kernel stage (as required by Linux)
 174          */
 175         setbits_le32(&scu_regs->sacr, 0xfff);
 176
 177         /* Configure the L2 controller to make SDRAM start at 0 */
 178 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 179         writel(0x2, &nic301_regs->remap);
 180 #else
 181         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 182         writel(0x1, &pl310->pl310_addr_filter_start);
 183 #endif
 184
 185         /* Add device descriptor to FPGA device table */
 186         socfpga_fpga_add();
 187         return 0;
 188 }