2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 static struct socfpga_system_manager *sysmgr_regs =
19 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
23 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
28 * DesignWare Ethernet initialization
30 #ifdef CONFIG_DESIGNWARE_ETH
31 int cpu_eth_init(bd_t *bis)
33 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
34 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
35 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
36 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
38 #error "Incorrect CONFIG_EMAC_BASE value!"
41 /* Initialize EMAC. This needs to be done at least once per boot. */
44 * Putting the EMAC controller to reset when configuring the PHY
45 * interface select at System Manager
47 socfpga_emac_reset(1);
49 /* Clearing emac0 PHY interface select to 0 */
50 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
51 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
53 /* configure to PHY interface select choosed */
54 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
55 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
57 /* Release the EMAC controller from reset */
58 socfpga_emac_reset(0);
60 /* initialize and register the emac */
61 return designware_initialize(CONFIG_EMAC_BASE,
62 CONFIG_PHY_INTERFACE_MODE);
68 * Initializes MMC controllers.
69 * to override, implement board_mmc_init()
71 int cpu_mmc_init(bd_t *bis)
73 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
74 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
78 #if defined(CONFIG_DISPLAY_CPUINFO)
80 * Print CPU information
82 int print_cpuinfo(void)
84 puts("CPU: Altera SoCFPGA Platform\n");
89 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
90 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
91 int overwrite_console(void)
99 * FPGA programming support for SoC FPGA Cyclone V
101 static Altera_desc altera_fpga[] = {
106 fast_passive_parallel,
107 /* No limitation as additional data will be ignored */
109 /* No device function table */
111 /* Base interface address specified in driver */
113 /* No cookie implementation */
118 /* add device descriptor to FPGA device table */
119 static void socfpga_fpga_add(void)
123 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
124 fpga_add(fpga_altera, &altera_fpga[i]);
127 static inline void socfpga_fpga_add(void) {}
130 int arch_cpu_init(void)
133 * If the HW watchdog is NOT enabled, make sure it is not running,
134 * for example because it was enabled in the preloader. This might
135 * trigger a watchdog-triggered reboot of Linux kernel later.
137 #ifndef CONFIG_HW_WATCHDOG
138 socfpga_watchdog_reset();
143 int misc_init_r(void)
145 /* Add device descriptor to FPGA device table */