2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/nic301.h>
16 #include <asm/arch/scu.h>
17 #include <asm/pl310.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static struct pl310_regs *const pl310 =
22 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
23 static struct socfpga_system_manager *sysmgr_regs =
24 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
25 static struct socfpga_reset_manager *reset_manager_base =
26 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
27 static struct nic301_registers *nic301_regs =
28 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
29 static struct scu_registers *scu_regs =
30 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
34 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
38 void enable_caches(void)
40 #ifndef CONFIG_SYS_ICACHE_OFF
43 #ifndef CONFIG_SYS_DCACHE_OFF
49 * DesignWare Ethernet initialization
51 #ifdef CONFIG_DESIGNWARE_ETH
52 int cpu_eth_init(bd_t *bis)
54 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
55 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
56 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
57 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
59 #error "Incorrect CONFIG_EMAC_BASE value!"
62 /* Initialize EMAC. This needs to be done at least once per boot. */
65 * Putting the EMAC controller to reset when configuring the PHY
66 * interface select at System Manager
68 socfpga_emac_reset(1);
70 /* Clearing emac0 PHY interface select to 0 */
71 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
72 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
74 /* configure to PHY interface select choosed */
75 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
76 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
78 /* Release the EMAC controller from reset */
79 socfpga_emac_reset(0);
81 /* initialize and register the emac */
82 return designware_initialize(CONFIG_EMAC_BASE,
83 CONFIG_PHY_INTERFACE_MODE);
89 * Initializes MMC controllers.
90 * to override, implement board_mmc_init()
92 int cpu_mmc_init(bd_t *bis)
94 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
95 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
99 #if defined(CONFIG_DISPLAY_CPUINFO)
101 * Print CPU information
103 int print_cpuinfo(void)
105 puts("CPU: Altera SoCFPGA Platform\n");
110 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
111 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
112 int overwrite_console(void)
120 * FPGA programming support for SoC FPGA Cyclone V
122 static Altera_desc altera_fpga[] = {
127 fast_passive_parallel,
128 /* No limitation as additional data will be ignored */
130 /* No device function table */
132 /* Base interface address specified in driver */
134 /* No cookie implementation */
139 /* add device descriptor to FPGA device table */
140 static void socfpga_fpga_add(void)
144 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
145 fpga_add(fpga_altera, &altera_fpga[i]);
148 static inline void socfpga_fpga_add(void) {}
151 int arch_cpu_init(void)
154 * If the HW watchdog is NOT enabled, make sure it is not running,
155 * for example because it was enabled in the preloader. This might
156 * trigger a watchdog-triggered reboot of Linux kernel later.
158 #ifndef CONFIG_HW_WATCHDOG
159 socfpga_watchdog_reset();
165 * Convert all NIC-301 AMBA slaves from secure to non-secure
167 static void socfpga_nic301_slave_ns(void)
169 writel(0x1, &nic301_regs->lwhps2fpgaregs);
170 writel(0x1, &nic301_regs->hps2fpgaregs);
171 writel(0x1, &nic301_regs->acp);
172 writel(0x1, &nic301_regs->rom);
173 writel(0x1, &nic301_regs->ocram);
174 writel(0x1, &nic301_regs->sdrdata);
177 static uint32_t iswgrp_handoff[8];
179 int arch_early_init_r(void)
182 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
183 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
185 socfpga_bridges_reset(1);
186 socfpga_nic301_slave_ns();
189 * Private components security:
190 * U-Boot : configure private timer, global timer and cpu component
191 * access as non secure for kernel stage (as required by Linux)
193 setbits_le32(&scu_regs->sacr, 0xfff);
195 /* Configure the L2 controller to make SDRAM start at 0 */
196 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
197 writel(0x2, &nic301_regs->remap);
199 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
200 writel(0x1, &pl310->pl310_addr_filter_start);
203 /* Add device descriptor to FPGA device table */
208 static void socfpga_sdram_apply_static_cfg(void)
210 const uint32_t staticcfg = SOCFPGA_SDR_ADDRESS + 0x505c;
211 const uint32_t applymask = 0x8;
212 uint32_t val = readl(staticcfg) | applymask;
215 * SDRAM staticcfg register specific:
216 * When applying the register setting, the CPU must not access
217 * SDRAM. Luckily for us, we can abuse i-cache here to help us
218 * circumvent the SDRAM access issue. The idea is to make sure
219 * that the code is in one full i-cache line by branching past
220 * it and back. Once it is in the i-cache, we execute the core
221 * of the code and apply the register settings.
223 * The code below uses 7 instructions, while the Cortex-A9 has
224 * 32-byte cachelines, thus the limit is 8 instructions total.
235 : : "r"(val), "r"(staticcfg) : "memory", "cc");
238 int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
241 return CMD_RET_USAGE;
246 case 'e': /* Enable */
247 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
248 socfpga_sdram_apply_static_cfg();
249 writel(iswgrp_handoff[3], SOCFPGA_SDR_ADDRESS + 0x5080);
250 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
251 writel(iswgrp_handoff[1], &nic301_regs->remap);
253 case 'd': /* Disable */
254 writel(0, &sysmgr_regs->fpgaintfgrp_module);
255 writel(0, SOCFPGA_SDR_ADDRESS + 0x5080);
256 socfpga_sdram_apply_static_cfg();
257 writel(0, &reset_manager_base->brg_mod_reset);
258 writel(1, &nic301_regs->remap);
261 return CMD_RET_USAGE;
268 bridge, 2, 1, do_bridge,
269 "SoCFPGA HPS FPGA bridge control",
270 "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
271 "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"