arch/arm/cpu/armv7/socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <altera.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <asm/arch/system_manager.h>
  14 #include <asm/arch/dwmmc.h>
  15 #include <asm/arch/nic301.h>
  16 #include <asm/arch/scu.h>
  17 #include <asm/pl310.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static struct pl310_regs *const pl310 =
  22         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  23 static struct socfpga_system_manager *sysmgr_regs =
  24         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  25 static struct nic301_registers *nic301_regs =
  26         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  27 static struct scu_registers *scu_regs =
  28         (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
  29
  30 int dram_init(void)
  31 {
  32         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  33         return 0;
  34 }
  35
  36 void enable_caches(void)
  37 {
  38 #ifndef CONFIG_SYS_ICACHE_OFF
  39         icache_enable();
  40 #endif
  41 #ifndef CONFIG_SYS_DCACHE_OFF
  42         dcache_enable();
  43 #endif
  44 }
  45
  46 /*
  47  * DesignWare Ethernet initialization
  48  */
  49 #ifdef CONFIG_DESIGNWARE_ETH
  50 int cpu_eth_init(bd_t *bis)
  51 {
  52 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  53         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  54 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  55         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  56 #else
  57 #error "Incorrect CONFIG_EMAC_BASE value!"
  58 #endif
  59
  60         /* Initialize EMAC. This needs to be done at least once per boot. */
  61
  62         /*
  63          * Putting the EMAC controller to reset when configuring the PHY
  64          * interface select at System Manager
  65          */
  66         socfpga_emac_reset(1);
  67
  68         /* Clearing emac0 PHY interface select to 0 */
  69         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  70                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  71
  72         /* configure to PHY interface select choosed */
  73         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  74                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  75
  76         /* Release the EMAC controller from reset */
  77         socfpga_emac_reset(0);
  78
  79         /* initialize and register the emac */
  80         return designware_initialize(CONFIG_EMAC_BASE,
  81                                      CONFIG_PHY_INTERFACE_MODE);
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_DWMMC
  86 /*
  87  * Initializes MMC controllers.
  88  * to override, implement board_mmc_init()
  89  */
  90 int cpu_mmc_init(bd_t *bis)
  91 {
  92         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  93                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
  94 }
  95 #endif
  96
  97 #if defined(CONFIG_DISPLAY_CPUINFO)
  98 /*
  99  * Print CPU information
 100  */
 101 int print_cpuinfo(void)
 102 {
 103         puts("CPU:   Altera SoCFPGA Platform\n");
 104         return 0;
 105 }
 106 #endif
 107
 108 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
 109 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 110 int overwrite_console(void)
 111 {
 112         return 0;
 113 }
 114 #endif
 115
 116 #ifdef CONFIG_FPGA
 117 /*
 118  * FPGA programming support for SoC FPGA Cyclone V
 119  */
 120 static Altera_desc altera_fpga[] = {
 121         {
 122                 /* Family */
 123                 Altera_SoCFPGA,
 124                 /* Interface type */
 125                 fast_passive_parallel,
 126                 /* No limitation as additional data will be ignored */
 127                 -1,
 128                 /* No device function table */
 129                 NULL,
 130                 /* Base interface address specified in driver */
 131                 NULL,
 132                 /* No cookie implementation */
 133                 0
 134         },
 135 };
 136
 137 /* add device descriptor to FPGA device table */
 138 static void socfpga_fpga_add(void)
 139 {
 140         int i;
 141         fpga_init();
 142         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 143                 fpga_add(fpga_altera, &altera_fpga[i]);
 144 }
 145 #else
 146 static inline void socfpga_fpga_add(void) {}
 147 #endif
 148
 149 int arch_cpu_init(void)
 150 {
 151         /*
 152          * If the HW watchdog is NOT enabled, make sure it is not running,
 153          * for example because it was enabled in the preloader. This might
 154          * trigger a watchdog-triggered reboot of Linux kernel later.
 155          */
 156 #ifndef CONFIG_HW_WATCHDOG
 157         socfpga_watchdog_reset();
 158 #endif
 159         return 0;
 160 }
 161
 162 /*
 163  * Convert all NIC-301 AMBA slaves from secure to non-secure
 164  */
 165 static void socfpga_nic301_slave_ns(void)
 166 {
 167         writel(0x1, &nic301_regs->lwhps2fpgaregs);
 168         writel(0x1, &nic301_regs->hps2fpgaregs);
 169         writel(0x1, &nic301_regs->acp);
 170         writel(0x1, &nic301_regs->rom);
 171         writel(0x1, &nic301_regs->ocram);
 172         writel(0x1, &nic301_regs->sdrdata);
 173 }
 174
 175 int misc_init_r(void)
 176 {
 177         socfpga_bridges_reset(1);
 178         socfpga_nic301_slave_ns();
 179
 180         /*
 181          * Private components security:
 182          * U-Boot : configure private timer, global timer and cpu component
 183          * access as non secure for kernel stage (as required by Linux)
 184          */
 185         setbits_le32(&scu_regs->sacr, 0xfff);
 186
 187         /* Configure the L2 controller to make SDRAM start at 0 */
 188 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 189         writel(0x2, &nic301_regs->remap);
 190 #else
 191         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 192         writel(0x1, &pl310->pl310_addr_filter_start);
 193 #endif
 194
 195         /* Add device descriptor to FPGA device table */
 196         socfpga_fpga_add();
 197         return 0;
 198 }