arch/arm/cpu/armv7/socfpga/misc.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <altera.h>
  10 #include <miiphy.h>
  11 #include <netdev.h>
  12 #include <asm/arch/reset_manager.h>
  13 #include <asm/arch/system_manager.h>
  14 #include <asm/arch/dwmmc.h>
  15 #include <asm/arch/nic301.h>
  16 #include <asm/pl310.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct pl310_regs *const pl310 =
  21         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  22 static struct socfpga_system_manager *sysmgr_regs =
  23         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  24 static struct nic301_registers *nic301_regs =
  25         (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
  26
  27 int dram_init(void)
  28 {
  29         gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  30         return 0;
  31 }
  32
  33 /*
  34  * DesignWare Ethernet initialization
  35  */
  36 #ifdef CONFIG_DESIGNWARE_ETH
  37 int cpu_eth_init(bd_t *bis)
  38 {
  39 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
  40         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
  41 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
  42         const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
  43 #else
  44 #error "Incorrect CONFIG_EMAC_BASE value!"
  45 #endif
  46
  47         /* Initialize EMAC. This needs to be done at least once per boot. */
  48
  49         /*
  50          * Putting the EMAC controller to reset when configuring the PHY
  51          * interface select at System Manager
  52          */
  53         socfpga_emac_reset(1);
  54
  55         /* Clearing emac0 PHY interface select to 0 */
  56         clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
  57                      SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
  58
  59         /* configure to PHY interface select choosed */
  60         setbits_le32(&sysmgr_regs->emacgrp_ctrl,
  61                      SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
  62
  63         /* Release the EMAC controller from reset */
  64         socfpga_emac_reset(0);
  65
  66         /* initialize and register the emac */
  67         return designware_initialize(CONFIG_EMAC_BASE,
  68                                      CONFIG_PHY_INTERFACE_MODE);
  69 }
  70 #endif
  71
  72 #ifdef CONFIG_DWMMC
  73 /*
  74  * Initializes MMC controllers.
  75  * to override, implement board_mmc_init()
  76  */
  77 int cpu_mmc_init(bd_t *bis)
  78 {
  79         return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
  80                                   CONFIG_HPS_SDMMC_BUSWIDTH, 0);
  81 }
  82 #endif
  83
  84 #if defined(CONFIG_DISPLAY_CPUINFO)
  85 /*
  86  * Print CPU information
  87  */
  88 int print_cpuinfo(void)
  89 {
  90         puts("CPU:   Altera SoCFPGA Platform\n");
  91         return 0;
  92 }
  93 #endif
  94
  95 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  96 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  97 int overwrite_console(void)
  98 {
  99         return 0;
 100 }
 101 #endif
 102
 103 #ifdef CONFIG_FPGA
 104 /*
 105  * FPGA programming support for SoC FPGA Cyclone V
 106  */
 107 static Altera_desc altera_fpga[] = {
 108         {
 109                 /* Family */
 110                 Altera_SoCFPGA,
 111                 /* Interface type */
 112                 fast_passive_parallel,
 113                 /* No limitation as additional data will be ignored */
 114                 -1,
 115                 /* No device function table */
 116                 NULL,
 117                 /* Base interface address specified in driver */
 118                 NULL,
 119                 /* No cookie implementation */
 120                 0
 121         },
 122 };
 123
 124 /* add device descriptor to FPGA device table */
 125 static void socfpga_fpga_add(void)
 126 {
 127         int i;
 128         fpga_init();
 129         for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
 130                 fpga_add(fpga_altera, &altera_fpga[i]);
 131 }
 132 #else
 133 static inline void socfpga_fpga_add(void) {}
 134 #endif
 135
 136 int arch_cpu_init(void)
 137 {
 138         /*
 139          * If the HW watchdog is NOT enabled, make sure it is not running,
 140          * for example because it was enabled in the preloader. This might
 141          * trigger a watchdog-triggered reboot of Linux kernel later.
 142          */
 143 #ifndef CONFIG_HW_WATCHDOG
 144         socfpga_watchdog_reset();
 145 #endif
 146         return 0;
 147 }
 148
 149 int misc_init_r(void)
 150 {
 151         /* Configure the L2 controller to make SDRAM start at 0 */
 152 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 153         writel(0x2, &nic301_regs->remap);
 154 #else
 155         writel(0x1, &nic301_regs->remap);       /* remap.mpuzero */
 156         writel(0x1, &pl310->pl310_addr_filter_start);
 157 #endif
 158
 159         /* Add device descriptor to FPGA device table */
 160         socfpga_fpga_add();
 161         return 0;
 162 }