2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/reset_manager.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 static const struct socfpga_reset_manager *reset_manager_base =
15 (void *)SOCFPGA_RSTMGR_ADDRESS;
17 /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
18 void socfpga_watchdog_reset(void)
20 /* assert reset for watchdog */
21 setbits_le32(&reset_manager_base->per_mod_reset,
22 1 << RSTMGR_PERMODRST_L4WD0_LSB);
24 /* deassert watchdog from reset (watchdog in not running state) */
25 clrbits_le32(&reset_manager_base->per_mod_reset,
26 1 << RSTMGR_PERMODRST_L4WD0_LSB);
30 * Write the reset manager register to cause reset
32 void reset_cpu(ulong addr)
34 /* request a warm reset */
35 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
36 &reset_manager_base->ctrl);
38 * infinite loop here as watchdog will trigger and reset
46 * Release peripherals from reset based on handoff
48 void reset_deassert_peripherals_handoff(void)
50 writel(0, &reset_manager_base->per_mod_reset);