2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
19 #include <asm/system.h>
20 #include <linux/linkage.h>
24 ldr pc, _undefined_instruction
25 ldr pc, _software_interrupt
26 ldr pc, _prefetch_abort
31 #ifdef CONFIG_SPL_BUILD
32 _undefined_instruction: .word _undefined_instruction
33 _software_interrupt: .word _software_interrupt
34 _prefetch_abort: .word _prefetch_abort
35 _data_abort: .word _data_abort
36 _not_used: .word _not_used
39 _pad: .word 0x12345678 /* now 16*4=64 */
41 _undefined_instruction: .word undefined_instruction
42 _software_interrupt: .word software_interrupt
43 _prefetch_abort: .word prefetch_abort
44 _data_abort: .word data_abort
45 _not_used: .word not_used
48 _pad: .word 0x12345678 /* now 16*4=64 */
49 #endif /* CONFIG_SPL_BUILD */
54 .balignl 16,0xdeadbeef
55 /*************************************************************************
57 * Startup Code (reset vector)
59 * do important init only if we don't start from memory!
60 * setup Memory and board specific bits prior to relocation.
61 * relocate armboot to ram
64 *************************************************************************/
71 * These are defined in the board-specific linker script.
75 .word __bss_start - _start
79 .word __bss_end - _start
86 /* IRQ stack memory (calculated at run-time) */
87 .globl IRQ_STACK_START
91 /* IRQ stack memory (calculated at run-time) */
92 .globl FIQ_STACK_START
97 /* IRQ stack memory (calculated at run-time) + 8 bytes */
98 .globl IRQ_STACK_START_IN
103 * the actual reset code
109 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
110 * except if in HYP mode already
113 and r1, r0, #0x1f @ mask mode bits
114 teq r1, #0x1a @ test for HYP mode
115 bicne r0, r0, #0x1f @ clear all mode bits
116 orrne r0, r0, #0x13 @ set SVC mode
117 orr r0, r0, #0xc0 @ disable FIQ and IRQ
122 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
123 * Continue to use ROM code vector only in OMAP4 spl)
125 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
126 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
127 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
128 bic r0, #CR_V @ V = 0
129 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
131 /* Set vector address in CP15 VBAR register */
133 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
136 /* the mask ROM code should have PLL and others stable */
137 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
144 /*------------------------------------------------------------------------------*/
146 ENTRY(c_runtime_cpu_setup)
148 * If I-cache is enabled invalidate it
150 #ifndef CONFIG_SYS_ICACHE_OFF
151 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
152 mcr p15, 0, r0, c7, c10, 4 @ DSB
153 mcr p15, 0, r0, c7, c5, 4 @ ISB
158 /* Set vector address in CP15 VBAR register */
160 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
164 ENDPROC(c_runtime_cpu_setup)
166 /*************************************************************************
168 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
169 * __attribute__((weak));
171 * Stack pointer is not yet initialized at this moment
172 * Don't save anything to stack even if compiled with -O0
174 *************************************************************************/
175 ENTRY(save_boot_params)
176 bx lr @ back to my caller
177 ENDPROC(save_boot_params)
178 .weak save_boot_params
180 /*************************************************************************
184 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
185 * CONFIG_SYS_ICACHE_OFF is defined.
187 *************************************************************************/
192 mov r0, #0 @ set up for MCR
193 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
194 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
195 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
196 mcr p15, 0, r0, c7, c10, 4 @ DSB
197 mcr p15, 0, r0, c7, c5, 4 @ ISB
200 * disable MMU stuff and caches
202 mrc p15, 0, r0, c1, c0, 0
203 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
204 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
205 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
206 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
207 #ifdef CONFIG_SYS_ICACHE_OFF
208 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
210 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
212 mcr p15, 0, r0, c1, c0, 0
214 #ifdef CONFIG_ARM_ERRATA_716044
215 mrc p15, 0, r0, c1, c0, 0 @ read system control register
216 orr r0, r0, #1 << 11 @ set bit #11
217 mcr p15, 0, r0, c1, c0, 0 @ write system control register
220 #ifdef CONFIG_ARM_ERRATA_742230
221 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
222 orr r0, r0, #1 << 4 @ set bit #4
223 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
226 #ifdef CONFIG_ARM_ERRATA_743622
227 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
228 orr r0, r0, #1 << 6 @ set bit #6
229 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
232 #ifdef CONFIG_ARM_ERRATA_751472
233 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
234 orr r0, r0, #1 << 11 @ set bit #11
235 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
238 mov pc, lr @ back to my caller
239 ENDPROC(cpu_init_cp15)
241 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
242 /*************************************************************************
244 * CPU_init_critical registers
246 * setup important registers
247 * setup memory timing
249 *************************************************************************/
252 * Jump to board specific initialization...
253 * The Mask ROM will have already initialized
254 * basic memory. Go here to bump up clock rate and handle
255 * wake up conditions.
257 b lowlevel_init @ go setup pll,mux,memory
258 ENDPROC(cpu_init_crit)
261 #ifndef CONFIG_SPL_BUILD
263 *************************************************************************
267 *************************************************************************
272 #define S_FRAME_SIZE 72
294 #define MODE_SVC 0x13
298 * use bad_save_user_regs for abort/prefetch/undef/swi ...
299 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
302 .macro bad_save_user_regs
303 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
305 stmia sp, {r0 - r12} @ Save user registers (now in
307 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
309 ldmia r2, {r2 - r3} @ get values for "aborted" pc
310 @ and cpsr (into parm regs)
311 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
315 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
316 mov r0, sp @ save current stack into r0
320 .macro irq_save_user_regs
321 sub sp, sp, #S_FRAME_SIZE
322 stmia sp, {r0 - r12} @ Calling r0-r12
323 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
324 @ a reserved stack spot would
326 stmdb r8, {sp, lr}^ @ Calling SP, LR
327 str lr, [r8, #0] @ Save calling PC
329 str r6, [r8, #4] @ Save CPSR
330 str r0, [r8, #8] @ Save OLD_R0
334 .macro irq_restore_user_regs
335 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
337 ldr lr, [sp, #S_PC] @ Get PC
338 add sp, sp, #S_FRAME_SIZE
339 subs pc, lr, #4 @ return & move spsr_svc into
344 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
347 str lr, [r13] @ save caller lr in position 0
349 mrs lr, spsr @ get the spsr
350 str lr, [r13, #4] @ save spsr in position 1 of
353 mov r13, #MODE_SVC @ prepare SVC-Mode
355 msr spsr, r13 @ switch modes, make sure
357 mov lr, pc @ capture return pc
358 movs pc, lr @ jump to next instruction &
362 .macro get_bad_stack_swi
363 sub r13, r13, #4 @ space on current stack for
365 str r0, [r13] @ save R0's value.
366 ldr r0, IRQ_STACK_START_IN @ get data regions start
367 @ spots for abort stack
368 str lr, [r0] @ save caller lr in position 0
370 mrs lr, spsr @ get the spsr
371 str lr, [r0, #4] @ save spsr in position 1 of
373 ldr lr, [r0] @ restore lr
374 ldr r0, [r13] @ restore r0
375 add r13, r13, #4 @ pop stack entry
378 .macro get_irq_stack @ setup IRQ stack
379 ldr sp, IRQ_STACK_START
382 .macro get_fiq_stack @ setup FIQ stack
383 ldr sp, FIQ_STACK_START
390 undefined_instruction:
393 bl do_undefined_instruction
399 bl do_software_interrupt
419 #ifdef CONFIG_USE_IRQ
426 irq_restore_user_regs
431 /* someone ought to write a more effective fiq_save_user_regs */
434 irq_restore_user_regs
450 #endif /* CONFIG_USE_IRQ */
451 #endif /* CONFIG_SPL_BUILD */