2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Based on code by Carl van Schaik <carl@ok-labs.com>.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm/arch/cpu.h>
27 * SECURE_RAM to text_end :
28 * ._secure_text section
29 * text_end to ALIGN_PAGE(text_end):
31 * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
32 * 1kB of stack per CPU (4 CPUs max).
35 .pushsection ._secure.text, "ax"
39 #define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
40 #define TEN_MS (10 * ONE_MS)
42 .macro timer_wait reg, ticks
44 movw \reg, #(\ticks & 0xffff)
45 movt \reg, #(\ticks >> 16)
46 mcr p15, 0, \reg, c14, c2, 0
48 @ Enable physical timer, mask interrupt
50 mcr p15, 0, \reg, c14, c2, 1
51 @ Poll physical timer until ISTATUS is on
53 mrc p15, 0, \reg, c14, c2, 1
58 mcr p15, 0, \reg, c14, c2, 1
64 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
65 bic r5, r5, #1 @ Secure mode
66 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
69 mrc p15, 0, r4, c0, c0, 5 @ MPIDR
70 and r4, r4, #3 @ cpu number in cluster
71 mov r5, #400 @ 1kB of stack per CPU
74 adr r5, text_end @ end of text
75 add r5, r5, #0x2000 @ Skip two pages
76 lsr r5, r5, #12 @ Align to start of page
78 sub sp, r5, r4 @ here's our stack!
90 movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
91 movt r0, #(SUNXI_CPUCFG_BASE >> 16)
94 and r1, r1, #3 @ only care about first cluster
98 adr r6, _sunxi_cpu_entry
99 str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
101 @ Assert reset on target CPU
103 lsl r5, r1, #6 @ 64 bytes per CPU
104 add r5, r5, #0x40 @ Offset from base
105 add r5, r5, r0 @ CPU control block
106 str r6, [r5] @ Reset CPU
118 @ Release power clamp
125 timer_wait r1, TEN_MS
132 @ Deassert reset on target CPU
141 mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
149 mrc p15, 0, r0, c1, c0, 1
151 mcr p15, 0, r0, c1, c0, 1