arch/arm/cpu/armv7/sunxi/rsb.c

   1 /*
   2  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
   3  *
   4  * Based on allwinner u-boot sources rsb code which is:
   5  * (C) Copyright 2007-2013
   6  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   7  * lixiang <lixiang@allwinnertech.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <asm/arch/cpu.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/rsb.h>
  18
  19 static void rsb_cfg_io(void)
  20 {
  21         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
  22         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
  23         sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
  24         sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
  25         sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
  26         sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
  27 }
  28
  29 static void rsb_set_clk(void)
  30 {
  31         struct sunxi_rsb_reg * const rsb =
  32                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  33         u32 div = 0;
  34         u32 cd_odly = 0;
  35
  36         /* Source is Hosc24M, set RSB clk to 3Mhz */
  37         div = 24000000 / 3000000 / 2 - 1;
  38         cd_odly = div >> 1;
  39         if (!cd_odly)
  40                 cd_odly = 1;
  41
  42         writel((cd_odly << 8) | div, &rsb->ccr);
  43 }
  44
  45 void rsb_init(void)
  46 {
  47         struct sunxi_rsb_reg * const rsb =
  48                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  49
  50         rsb_cfg_io();
  51
  52         /* Enable RSB and PIO clk, and de-assert their resets */
  53         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
  54
  55         writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
  56         rsb_set_clk();
  57 }
  58
  59 static int rsb_await_trans(void)
  60 {
  61         struct sunxi_rsb_reg * const rsb =
  62                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  63         unsigned long tmo = timer_get_us() + 1000000;
  64         u32 stat;
  65         int ret;
  66
  67         while (1) {
  68                 stat = readl(&rsb->stat);
  69                 if (stat & RSB_STAT_LBSY_INT) {
  70                         ret = -EBUSY;
  71                         break;
  72                 }
  73                 if (stat & RSB_STAT_TERR_INT) {
  74                         ret = -EIO;
  75                         break;
  76                 }
  77                 if (stat & RSB_STAT_TOVER_INT) {
  78                         ret = 0;
  79                         break;
  80                 }
  81                 if (timer_get_us() > tmo) {
  82                         ret = -ETIME;
  83                         break;
  84                 }
  85         }
  86         writel(stat, &rsb->stat); /* Clear status bits */
  87
  88         return ret;
  89 }
  90
  91 int rsb_set_device_mode(u32 device_mode_data)
  92 {
  93         struct sunxi_rsb_reg * const rsb =
  94                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
  95         unsigned long tmo = timer_get_us() + 1000000;
  96
  97         writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
  98
  99         while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
 100                 if (timer_get_us() > tmo)
 101                         return -ETIME;
 102         }
 103
 104         return rsb_await_trans();
 105 }
 106
 107 static int rsb_do_trans(void)
 108 {
 109         struct sunxi_rsb_reg * const rsb =
 110                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 111
 112         setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
 113         return rsb_await_trans();
 114 }
 115
 116 int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
 117 {
 118         struct sunxi_rsb_reg * const rsb =
 119                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 120
 121         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
 122                RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
 123         writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
 124
 125         return rsb_do_trans();
 126 }
 127
 128 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
 129 {
 130         struct sunxi_rsb_reg * const rsb =
 131                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 132
 133         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
 134         writel(reg_addr, &rsb->addr);
 135         writel(data, &rsb->data);
 136         writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
 137
 138         return rsb_do_trans();
 139 }
 140
 141 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
 142 {
 143         struct sunxi_rsb_reg * const rsb =
 144                 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
 145         int ret;
 146
 147         writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
 148         writel(reg_addr, &rsb->addr);
 149         writel(RSB_CMD_BYTE_READ, &rsb->cmd);
 150
 151         ret = rsb_do_trans();
 152         if (ret)
 153                 return ret;
 154
 155         *data = readl(&rsb->data) & 0xff;
 156
 157         return 0;
 158 }