2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/sc-regs.h>
10 #include <asm/arch/sg-regs.h>
12 #undef DPLL_SSC_RATE_1PER
20 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
21 * to FOUT (DPLLCTRL.bit[29:20])
23 tmp = readl(SC_DPLLCTRL);
25 #if CONFIG_DDR_FREQ == 1600
27 #elif CONFIG_DDR_FREQ == 1333
30 # error "Unknown frequency"
33 #if defined(DPLL_SSC_RATE_1PER)
34 tmp &= ~SC_DPLLCTRL_SSC_RATE;
36 tmp |= SC_DPLLCTRL_SSC_RATE;
38 writel(tmp, SC_DPLLCTRL);
40 tmp = readl(SC_DPLLCTRL2);
41 tmp |= SC_DPLLCTRL2_NRSTDS;
42 writel(tmp, SC_DPLLCTRL2);
47 u32 tmp, clk_mode_upll, clk_mode_axosel;
49 tmp = readl(SG_PINMON0);
50 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
51 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
53 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
54 tmp = readl(SC_UPLLCTRL);
56 writel(tmp, SC_UPLLCTRL);
58 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
59 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
60 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
65 /* AXO: default 24.576MHz */
71 writel(tmp, SC_UPLLCTRL);
73 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
75 writel(tmp, SC_UPLLCTRL);
80 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
82 writel(tmp, SC_UPLLCTRL);
87 u32 tmp, clk_mode_axosel;
89 tmp = readl(SG_PINMON0);
90 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
92 /* set 1 to VPLA27WP and VPLA27WP */
93 tmp = readl(SC_VPLL27ACTRL);
95 writel(tmp, SC_VPLL27ACTRL);
96 tmp = readl(SC_VPLL27BCTRL);
98 writel(tmp, SC_VPLL27BCTRL);
100 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
101 tmp = readl(SC_VPLL27ACTRL3);
103 writel(tmp, SC_VPLL27ACTRL3);
104 tmp = readl(SC_VPLL27BCTRL3);
106 writel(tmp, SC_VPLL27BCTRL3);
108 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
109 tmp = readl(SC_VPLL27ACTRL2);
111 writel(tmp, SC_VPLL27ACTRL2);
112 tmp = readl(SC_VPLL27BCTRL2);
114 writel(tmp, SC_VPLL27BCTRL2);
116 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
117 tmp = readl(SC_VPLL27ACTRL2);
120 writel(tmp, SC_VPLL27ACTRL2);
121 tmp = readl(SC_VPLL27BCTRL2);
124 writel(tmp, SC_VPLL27BCTRL2);
126 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
127 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
129 tmp = readl(SC_VPLL27ACTRL3);
132 writel(tmp, SC_VPLL27ACTRL3);
133 tmp = readl(SC_VPLL27BCTRL3);
136 writel(tmp, SC_VPLL27BCTRL3);
138 /* AXO: default 24.576MHz */
139 tmp = readl(SC_VPLL27ACTRL3);
142 writel(tmp, SC_VPLL27ACTRL3);
143 tmp = readl(SC_VPLL27BCTRL3);
146 writel(tmp, SC_VPLL27BCTRL3);
149 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
150 tmp = readl(SC_VPLL27ACTRL3);
152 writel(tmp, SC_VPLL27ACTRL3);
153 tmp = readl(SC_VPLL27BCTRL3);
155 writel(tmp, SC_VPLL27BCTRL3);
160 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
161 tmp = readl(SC_VPLL27ACTRL2);
163 writel(tmp, SC_VPLL27ACTRL2);
164 tmp = readl(SC_VPLL27BCTRL2);
166 writel(tmp, SC_VPLL27BCTRL2);
168 /* set 0 to VPLA27WP and VPLA27WP */
169 tmp = readl(SC_VPLL27ACTRL);
171 writel(tmp, SC_VPLL27ACTRL);
172 tmp = readl(SC_VPLL27BCTRL);
174 writel(tmp, SC_VPLL27BCTRL);
184 * Wait 500 usec until dpll get stable
185 * We wait 10 usec in upll_init() and vpll_init()
186 * so 20 usec can be saved here.