2 * Copyright (C) 2011-2014 Panasonic Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/sc-regs.h>
10 #include <asm/arch/sg-regs.h>
12 static void dpll_init(void)
16 * Set DPLL SSC parameters for DPLLCTRL3
19 * [10] FREFSEL_TEST 0x1
24 tmp = readl(SC_DPLLCTRL3);
27 writel(tmp, SC_DPLLCTRL3);
30 * Set DPLL SSC parameters for DPLLCTRL
32 * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
33 * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
35 tmp = readl(SC_DPLLCTRL);
37 #ifdef CONFIG_DPLL_SSC_RATE_1PER
42 writel(tmp, SC_DPLLCTRL);
45 * Set DPLL SSC parameters for DPLLCTRL2
48 * [26:20] SSC_M 79 (0x4f)
49 * [19:0] SSC_K 964689 (0xeb851)
51 tmp = readl(SC_DPLLCTRL2);
54 writel(tmp, SC_DPLLCTRL2);
57 static void upll_init(void)
59 u32 tmp, clk_mode_upll, clk_mode_axosel;
61 tmp = readl(SG_PINMON0);
62 clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
63 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
65 /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
66 tmp = readl(SC_UPLLCTRL);
68 writel(tmp, SC_UPLLCTRL);
70 if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
71 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
72 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
77 /* AXO: default 24.576MHz */
83 writel(tmp, SC_UPLLCTRL);
85 /* set 1 to K_LD(UPLLCTRL.bit[27]) */
87 writel(tmp, SC_UPLLCTRL);
92 /* set 1 to SNRT(UPLLCTRL.bit[28]) */
94 writel(tmp, SC_UPLLCTRL);
97 static void vpll_init(void)
99 u32 tmp, clk_mode_axosel;
101 tmp = readl(SG_PINMON0);
102 clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
104 /* set 1 to VPLA27WP and VPLA27WP */
105 tmp = readl(SC_VPLL27ACTRL);
107 writel(tmp, SC_VPLL27ACTRL);
108 tmp = readl(SC_VPLL27BCTRL);
110 writel(tmp, SC_VPLL27BCTRL);
112 /* Set 0 to VPLA_K_LD and VPLB_K_LD */
113 tmp = readl(SC_VPLL27ACTRL3);
115 writel(tmp, SC_VPLL27ACTRL3);
116 tmp = readl(SC_VPLL27BCTRL3);
118 writel(tmp, SC_VPLL27BCTRL3);
120 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
121 tmp = readl(SC_VPLL27ACTRL2);
123 writel(tmp, SC_VPLL27ACTRL2);
124 tmp = readl(SC_VPLL27BCTRL2);
126 writel(tmp, SC_VPLL27BCTRL2);
128 /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
129 tmp = readl(SC_VPLL27ACTRL2);
132 writel(tmp, SC_VPLL27ACTRL2);
133 tmp = readl(SC_VPLL27BCTRL2);
136 writel(tmp, SC_VPLL27BCTRL2);
138 if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
139 clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
141 tmp = readl(SC_VPLL27ACTRL3);
144 writel(tmp, SC_VPLL27ACTRL3);
145 tmp = readl(SC_VPLL27BCTRL3);
148 writel(tmp, SC_VPLL27BCTRL3);
150 /* AXO: default 24.576MHz */
151 tmp = readl(SC_VPLL27ACTRL3);
154 writel(tmp, SC_VPLL27ACTRL3);
155 tmp = readl(SC_VPLL27BCTRL3);
158 writel(tmp, SC_VPLL27BCTRL3);
161 /* Set 1 to VPLA_K_LD and VPLB_K_LD */
162 tmp = readl(SC_VPLL27ACTRL3);
164 writel(tmp, SC_VPLL27ACTRL3);
165 tmp = readl(SC_VPLL27BCTRL3);
167 writel(tmp, SC_VPLL27BCTRL3);
172 /* Set 0 to VPLA_SNRST and VPLB_SNRST */
173 tmp = readl(SC_VPLL27ACTRL2);
175 writel(tmp, SC_VPLL27ACTRL2);
176 tmp = readl(SC_VPLL27BCTRL2);
178 writel(tmp, SC_VPLL27BCTRL2);
180 /* set 0 to VPLA27WP and VPLA27WP */
181 tmp = readl(SC_VPLL27ACTRL);
183 writel(tmp, SC_VPLL27ACTRL);
184 tmp = readl(SC_VPLL27BCTRL);
186 writel(tmp, SC_VPLL27BCTRL);
196 * Wait 500 usec until dpll get stable
197 * We wait 10 usec in upll_init() and vpll_init()
198 * so 20 usec can be saved here.