3 * Kamil Lulko, <rev13@wp.pl>
5 * Copyright 2015 ATS Advanced Telematics Systems GmbH
6 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/stm32.h>
18 #define RCC_CR_HSION (1 << 0)
19 #define RCC_CR_HSEON (1 << 16)
20 #define RCC_CR_HSERDY (1 << 17)
21 #define RCC_CR_HSEBYP (1 << 18)
22 #define RCC_CR_CSSON (1 << 19)
23 #define RCC_CR_PLLON (1 << 24)
24 #define RCC_CR_PLLRDY (1 << 25)
26 #define RCC_CFGR_PLLMUL_MASK 0x3C0000
27 #define RCC_CFGR_PLLMUL_SHIFT 18
28 #define RCC_CFGR_PLLSRC_HSE (1 << 16)
30 #define RCC_CFGR_AHB_PSC_MASK 0xF0
31 #define RCC_CFGR_APB1_PSC_MASK 0x700
32 #define RCC_CFGR_APB2_PSC_MASK 0x3800
33 #define RCC_CFGR_SW0 (1 << 0)
34 #define RCC_CFGR_SW1 (1 << 1)
35 #define RCC_CFGR_SW_MASK 0x3
36 #define RCC_CFGR_SW_HSI 0
37 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
38 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
39 #define RCC_CFGR_SWS0 (1 << 2)
40 #define RCC_CFGR_SWS1 (1 << 3)
41 #define RCC_CFGR_SWS_MASK 0xC
42 #define RCC_CFGR_SWS_HSI 0
43 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
44 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
45 #define RCC_CFGR_HPRE_SHIFT 4
46 #define RCC_CFGR_PPRE1_SHIFT 8
47 #define RCC_CFGR_PPRE2_SHIFT 11
49 #define RCC_APB1ENR_PWREN (1 << 28)
51 #define PWR_CR_VOS0 (1 << 14)
52 #define PWR_CR_VOS1 (1 << 15)
53 #define PWR_CR_VOS_MASK 0xC000
54 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
55 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
56 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
58 #define FLASH_ACR_WS(n) n
59 #define FLASH_ACR_PRFTEN (1 << 8)
60 #define FLASH_ACR_ICEN (1 << 9)
61 #define FLASH_ACR_DCEN (1 << 10)
73 #define AHB_PSC_16 0xB
74 #define AHB_PSC_64 0xC
75 #define AHB_PSC_128 0xD
76 #define AHB_PSC_256 0xE
77 #define AHB_PSC_512 0xF
83 #define APB_PSC_16 0x7
85 #if !defined(CONFIG_STM32_HSE_HZ)
86 #error "CONFIG_STM32_HSE_HZ not defined!"
88 #if (CONFIG_STM32_HSE_HZ == 8000000)
89 #define RCC_CFGR_PLLMUL_CFG 0x7
90 struct psc psc_hse = {
92 .apb1_psc = APB_PSC_2,
96 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
100 int configure_clocks(void)
102 /* Reset RCC configuration */
103 setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
104 writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
105 clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
107 clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
108 writel(0, &STM32_RCC->cir); /* Disable all interrupts */
110 /* Configure for HSE+PLL operation */
111 setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
112 while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
115 /* Enable high performance mode, System frequency up to 168 MHz */
116 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
117 writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
119 setbits_le32(&STM32_RCC->cfgr,
120 RCC_CFGR_PLLMUL_CFG << RCC_CFGR_PLLMUL_SHIFT);
121 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_PLLSRC_HSE);
122 setbits_le32(&STM32_RCC->cfgr, ((
123 psc_hse.ahb_psc << RCC_CFGR_HPRE_SHIFT)
124 | (psc_hse.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
125 | (psc_hse.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
127 setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
129 while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
132 /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
133 writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
134 | FLASH_ACR_DCEN, &STM32_FLASH->acr);
136 clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
137 setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
139 while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
146 unsigned long clock_get(enum clock clck)
150 /* PLL table lookups for clock computation */
151 u8 pll_mul_table[16] = {
152 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16
154 /* Prescaler table lookups for clock computation */
155 u8 ahb_psc_table[16] = {
156 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
158 u8 apb_psc_table[8] = {
159 0, 0, 0, 0, 1, 2, 3, 4
162 if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
165 pll = ((readl(&STM32_RCC->cfgr) & RCC_CFGR_PLLMUL_MASK)
166 >> RCC_CFGR_PLLMUL_SHIFT);
167 sysclk = CONFIG_STM32_HSE_HZ * pll_mul_table[pll];
175 shift = ahb_psc_table[(
176 (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
177 >> RCC_CFGR_HPRE_SHIFT)];
178 return sysclk >>= shift;
181 shift = apb_psc_table[(
182 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
183 >> RCC_CFGR_PPRE1_SHIFT)];
184 return sysclk >>= shift;
187 shift = apb_psc_table[(
188 (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
189 >> RCC_CFGR_PPRE2_SHIFT)];
190 return sysclk >>= shift;