3 * David Feng <fenghua@phytium.com.cn>
5 * This file is based on sample code from ARMv8 ARM.
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
13 #include <asm/macro.h>
14 #include <linux/linkage.h>
17 * void __asm_flush_dcache_level(level)
19 * clean and invalidate one level cache.
24 ENTRY(__asm_flush_dcache_level)
26 msr csselr_el1, x1 /* select cache level */
27 isb /* sync change of cssidr_el1 */
28 mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
29 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
30 add x2, x2, #4 /* x2 <- log2(cache line size) */
32 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
34 sub w4, w4, 1 /* round up log2(#ways + 1) */
35 clz w5, w4 /* bit position of #ways */
37 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
38 /* x1 <- cache level << 1 */
39 /* x2 <- line length offset */
40 /* x3 <- number of cache ways - 1 */
41 /* x4 <- number of cache sets - 1 */
42 /* x5 <- bit position of #ways */
45 mov x6, x3 /* x6 <- working copy of #ways */
48 orr x9, x1, x7 /* map way and level to cisw value */
50 orr x9, x9, x7 /* map set number to cisw value */
51 dc cisw, x9 /* clean & invalidate by set/way */
52 subs x6, x6, #1 /* decrement the way */
54 subs x4, x4, #1 /* decrement the set */
58 ENDPROC(__asm_flush_dcache_level)
61 * void __asm_flush_dcache_all(void)
63 * clean and invalidate all data cache by SET/WAY.
65 ENTRY(__asm_flush_dcache_all)
67 mrs x10, clidr_el1 /* read clidr_el1 */
69 and x11, x11, #0x7 /* x11 <- loc */
70 cbz x11, finished /* if loc is 0, exit */
72 mov x0, #0 /* start flush at cache level 0 */
73 /* x0 <- cache level */
74 /* x10 <- clidr_el1 */
76 /* x15 <- return address */
80 add x1, x1, x0 /* x0 <- tripled cache level */
82 and x1, x1, #7 /* x1 <- cache type */
84 b.lt skip /* skip if no cache or icache */
85 bl __asm_flush_dcache_level
87 add x0, x0, #1 /* increment cache level */
92 msr csselr_el1, x0 /* resotre csselr_el1 */
99 ENDPROC(__asm_flush_dcache_all)
102 * void __asm_flush_dcache_range(start, end)
104 * clean & invalidate data cache in the range
109 ENTRY(__asm_flush_dcache_range)
114 lsl x2, x2, x3 /* cache line size */
116 /* x2 <- minimal cache line size in cache system */
119 1: dc civac, x0 /* clean & invalidate data or unified cache */
125 ENDPROC(__asm_flush_dcache_range)
128 * void __asm_invalidate_icache_all(void)
130 * invalidate all tlb entries.
132 ENTRY(__asm_invalidate_icache_all)
136 ENDPROC(__asm_invalidate_icache_all)