2 * Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/soc.h>
13 #include <asm/global_data.h>
14 #include <asm/arch-fsl-layerscape/config.h>
16 #ifdef CONFIG_SYS_FSL_DDR
17 #include <fsl_ddr_sdram.h>
20 #ifdef CONFIG_CHAIN_OF_TRUST
21 #include <fsl_validate.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 bool soc_has_dp_ddr(void)
28 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
29 u32 svr = gur_in32(&gur->svr);
31 /* LS2085A has DP_DDR */
32 if (SVR_SOC_VER(svr) == SVR_LS2085A)
38 bool soc_has_aiop(void)
40 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
41 u32 svr = gur_in32(&gur->svr);
43 /* LS2085A has AIOP */
44 if (SVR_SOC_VER(svr) == SVR_LS2085A)
52 * This erratum requires setting a value to eddrtqcr1 to
53 * optimal the DDR performance.
55 static void erratum_a008336(void)
59 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
60 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
61 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
62 if (fsl_ddr_get_version(0) == 0x50200)
63 out_le32(eddrtqcr1, 0x63b30002);
65 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
66 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
67 if (fsl_ddr_get_version(0) == 0x50200)
68 out_le32(eddrtqcr1, 0x63b30002);
74 * This erratum requires a register write before being Memory
75 * controller 3 being enabled.
77 static void erratum_a008514(void)
81 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
82 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
83 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
84 out_le32(eddrtqcr1, 0x63b20002);
88 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
89 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
91 static unsigned long get_internval_val_mhz(void)
93 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
95 * interval is the number of platform cycles(MHz) between
96 * wake up events generated by EPU.
98 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
101 interval_mhz = simple_strtoul(interval, NULL, 10);
106 void erratum_a009635(void)
109 unsigned long interval_mhz = get_internval_val_mhz();
114 val = in_le32(DCSR_CGACRE5);
115 writel(val | 0x00000200, DCSR_CGACRE5);
117 val = in_le32(EPU_EPCMPR5);
118 writel(interval_mhz, EPU_EPCMPR5);
119 val = in_le32(EPU_EPCCR5);
120 writel(val | 0x82820000, EPU_EPCCR5);
121 val = in_le32(EPU_EPSMCR5);
122 writel(val | 0x002f0000, EPU_EPSMCR5);
123 val = in_le32(EPU_EPECR5);
124 writel(val | 0x20000000, EPU_EPECR5);
125 val = in_le32(EPU_EPGCR);
126 writel(val | 0x80000000, EPU_EPGCR);
128 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
130 static void erratum_rcw_src(void)
132 #if defined(CONFIG_SPL)
133 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
134 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
137 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
138 val &= ~DCFG_PORSR1_RCW_SRC;
139 val |= DCFG_PORSR1_RCW_SRC_NOR;
140 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
144 #define I2C_DEBUG_REG 0x6
145 #define I2C_GLITCH_EN 0x8
147 * This erratum requires setting glitch_en bit to enable
148 * digital glitch filter to improve clock stability.
150 static void erratum_a009203(void)
153 #ifdef CONFIG_SYS_I2C
154 #ifdef I2C1_BASE_ADDR
155 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
157 writeb(I2C_GLITCH_EN, ptr);
159 #ifdef I2C2_BASE_ADDR
160 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
162 writeb(I2C_GLITCH_EN, ptr);
164 #ifdef I2C3_BASE_ADDR
165 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
167 writeb(I2C_GLITCH_EN, ptr);
169 #ifdef I2C4_BASE_ADDR
170 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
172 writeb(I2C_GLITCH_EN, ptr);
176 void bypass_smmu(void)
179 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
180 out_le32(SMMU_SCR0, val);
181 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
182 out_le32(SMMU_NSCR0, val);
184 void fsl_lsch3_early_init_f(void)
187 init_early_memctl_regs(); /* tighten IFC timing */
191 #ifdef CONFIG_CHAIN_OF_TRUST
192 /* In case of Secure Boot, the IBR configures the SMMU
193 * to allow only Secure transactions.
194 * SMMU must be reset in bypass mode.
195 * Set the ClientPD bit and Clear the USFCFG Bit
197 if (fsl_check_boot_mode_secure() == 1)
202 #ifdef CONFIG_SCSI_AHCI_PLAT
205 struct ccsr_ahci __iomem *ccsr_ahci;
207 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
208 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
209 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
211 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
212 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
213 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
215 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
222 #elif defined(CONFIG_FSL_LSCH2)
223 #ifdef CONFIG_SCSI_AHCI_PLAT
226 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
228 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
229 out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
230 out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
231 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
233 ahci_init((void __iomem *)CONFIG_SYS_SATA);
240 static void erratum_a009929(void)
242 #ifdef CONFIG_SYS_FSL_ERRATUM_A009929
243 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
244 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
245 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
247 rstrqmr1 |= 0x00000400;
248 gur_out32(&gur->rstrqmr1, rstrqmr1);
249 writel(0x01000000, dcsr_cop_ccp);
254 * This erratum requires setting a value to eddrtqcr1 to optimal
255 * the DDR performance. The eddrtqcr1 register is in SCFG space
256 * of LS1043A and the offset is 0x157_020c.
258 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
259 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
260 #error A009660 and A008514 can not be both enabled.
263 static void erratum_a009660(void)
265 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
266 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
267 out_be32(eddrtqcr1, 0x63b20042);
271 static void erratum_a008850_early(void)
273 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
275 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
276 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
278 /* disables propagation of barrier transactions to DDRC from CCI400 */
279 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
281 /* disable the re-ordering in DDRC */
282 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
286 void erratum_a008850_post(void)
288 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
290 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
291 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
294 /* enable propagation of barrier transactions to DDRC from CCI400 */
295 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
297 /* enable the re-ordering in DDRC */
298 tmp = ddr_in32(&ddr->eor);
299 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
300 ddr_out32(&ddr->eor, tmp);
304 void fsl_lsch2_early_init_f(void)
306 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
307 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
309 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
310 enable_layerscape_ns_access();
313 #ifdef CONFIG_FSL_IFC
314 init_early_memctl_regs(); /* tighten IFC timing */
317 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
318 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
320 /* Make SEC reads and writes snoopable */
321 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
322 SCFG_SNPCNFGCR_SECWRSNP);
325 * Enable snoop requests and DVM message requests for
326 * Slave insterface S4 (A53 core cluster)
328 out_le32(&cci->slave[4].snoop_ctrl,
329 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
332 erratum_a008850_early(); /* part 1 of 2 */
338 #ifdef CONFIG_BOARD_LATE_INIT
339 int board_late_init(void)
341 #ifdef CONFIG_SCSI_AHCI_PLAT
344 #ifdef CONFIG_CHAIN_OF_TRUST
345 fsl_setenv_chain_of_trust();