2 * (C) Copyright 2014 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
16 mov x29, lr /* Save LR */
18 /* Set the SMMU page size in the sACR register */
21 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
24 /* Initialize GIC Secure Bank Status */
25 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
26 branch_if_slave x0, 1f
32 bl gic_init_secure_percpu
33 #elif defined(CONFIG_GICV2)
36 bl gic_init_secure_percpu
40 branch_if_master x0, x1, 2f
42 ldr x0, =secondary_boot_func
45 mov lr, x29 /* Restore LR */
47 ENDPROC(lowlevel_init)
49 /* Keep literals not used by the secondary boot code outside it */
52 /* Using 64 bit alignment since the spin table is accessed as data */
54 .global secondary_boot_code
55 /* Secondary Boot Code starts here */
59 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
62 ENTRY(secondary_boot_func)
65 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
66 * MPIDR[7:2] = AFF0_RES
67 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
68 * MPIDR[23:16] = AFF2_CLUSTERID
75 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
76 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
77 * until AFF2_CLUSTERID and AFF3 have non-zero values)
79 * LPID = MPIDR[15:8] | MPIDR[1:0]
84 orr x10, x2, x1, lsl #2 /* x10 has LPID */
85 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
87 * offset of the spin table element for this core from start of spin
88 * table (each elem is padded to 64 bytes)
92 /* physical address of this cpus spin table element */
95 str x9, [x11, #16] /* LPID */
97 str x4, [x11, #8] /* STATUS */
99 #if defined(CONFIG_GICV3)
100 gic_wait_for_interrupt_m x0
101 #elif defined(CONFIG_GICV2)
103 gic_wait_for_interrupt_m x0, w1
106 bl secondary_switch_to_el2
107 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
108 bl secondary_switch_to_el1
115 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
120 tbz x1, #25, cpu_is_le
121 rev x0, x0 /* BE to LE conversion */
123 br x0 /* branch to the given address */
124 ENDPROC(secondary_boot_func)
126 ENTRY(secondary_switch_to_el2)
127 switch_el x0, 1f, 0f, 0f
129 1: armv8_switch_to_el2_m x0
130 ENDPROC(secondary_switch_to_el2)
132 ENTRY(secondary_switch_to_el1)
133 switch_el x0, 0f, 1f, 0f
135 1: armv8_switch_to_el1_m x0, x1
136 ENDPROC(secondary_switch_to_el1)
138 /* Ensure that the literals used by the secondary boot code are
139 * assembled within it (this is required so that we can protect
140 * this area with a single memreserve region
144 /* 64 bit alignment for elements accessed as data */
146 .globl __secondary_boot_code_size
147 .type __secondary_boot_code_size, %object
148 /* Secondary Boot Code ends here */
149 __secondary_boot_code_size:
150 .quad .-secondary_boot_code