2 * Copyright 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch-fsl-lsch3/soc.h>
13 #include <asm/global_data.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 static void erratum_a008751(void)
19 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
20 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
22 writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
26 static void erratum_rcw_src(void)
28 #if defined(CONFIG_SPL)
29 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
30 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
33 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
34 val &= ~DCFG_PORSR1_RCW_SRC;
35 val |= DCFG_PORSR1_RCW_SRC_NOR;
36 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
40 #define I2C_DEBUG_REG 0x6
41 #define I2C_GLITCH_EN 0x8
43 * This erratum requires setting glitch_en bit to enable
44 * digital glitch filter to improve clock stability.
46 static void erratum_a009203(void)
51 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
53 writeb(I2C_GLITCH_EN, ptr);
56 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
58 writeb(I2C_GLITCH_EN, ptr);
61 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
63 writeb(I2C_GLITCH_EN, ptr);
66 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
68 writeb(I2C_GLITCH_EN, ptr);
73 void fsl_lsch3_early_init_f(void)
77 init_early_memctl_regs(); /* tighten IFC timing */
81 #ifdef CONFIG_SPL_BUILD
82 void board_init_f(ulong dummy)
84 /* Clear global data */
85 memset((void *)gd, 0, sizeof(gd_t));
91 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
98 memset(__bss_start, 0, __bss_end - __bss_start);
100 board_init_r(NULL, 0);
103 u32 spl_boot_device(void)
105 return BOOT_DEVICE_NAND;