2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 .word CONFIG_SYS_TEXT_BASE
70 * These are defined in the board-specific linker script.
81 /* IRQ stack memory (calculated at run-time) */
82 .globl IRQ_STACK_START
86 /* IRQ stack memory (calculated at run-time) */
87 .globl FIQ_STACK_START
92 /* IRQ stack memory (calculated at run-time) + 8 bytes */
93 .globl IRQ_STACK_START_IN
101 .globl _datarelrolocal_start
102 _datarelrolocal_start:
103 .word __datarelrolocal_start
105 .globl _datarellocal_start
107 .word __datarellocal_start
109 .globl _datarelro_start
111 .word __datarelro_start
122 * the actual reset code
127 * set the cpu to SVC32 mode
135 * we do sys-critical inits only at reboot,
136 * not when booting from ram!
138 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
141 * before relocating, we have to setup RAM timing
142 * because memory timing is board-dependend, you will
143 * find a lowlevel_init.S in your board directory.
148 /* Set stackpointer in internal RAM to call board_init_f */
150 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
154 /*------------------------------------------------------------------------------*/
157 * void relocate_code (addr_sp, gd, addr_moni)
159 * This "function" does not return, instead it continues in RAM
160 * after relocating the monitor code.
165 mov r4, r0 /* save addr_sp */
166 mov r5, r1 /* save addr of gd */
167 mov r6, r2 /* save addr of destination */
168 mov r7, r2 /* save addr of destination */
170 /* Set up the stack */
177 sub r2, r3, r2 /* r2 <- size of armboot */
178 add r2, r0, r2 /* r2 <- source end address */
183 ldmia r0!, {r9-r10} /* copy from source address [r0] */
184 stmia r6!, {r9-r10} /* copy to target address [r1] */
185 cmp r0, r2 /* until source end address [r2] */
188 #ifndef CONFIG_PRELOADER
189 /* fix got entries */
190 ldr r1, _TEXT_BASE /* Text base */
191 mov r0, r7 /* reloc addr */
192 ldr r2, _got_start /* addr in Flash */
193 ldr r3, _got_end /* addr in Flash */
209 now copy to sram the interrupt vector
222 #ifndef CONFIG_PRELOADER
225 ldr r3, _TEXT_BASE /* Text base */
226 mov r4, r7 /* reloc addr */
231 mov r2, #0x00000000 /* clear */
233 clbss_l:str r2, [r0] /* clear loop... */
243 * We are done. Do not return, instead branch to second part of board
244 * initialization, now running from RAM.
247 ldr r2, _board_init_r
249 add r2, r2, r7 /* position from board_init_r in RAM */
250 /* setup parameters for board_init_r */
251 mov r0, r5 /* gd_t */
252 mov r1, r7 /* dest_addr */
257 _board_init_r: .word board_init_r
260 *************************************************************************
262 * CPU_init_critical registers
264 * setup important registers
265 * setup memory timing
267 *************************************************************************
270 #define INTCON (0x01c00000+0x200000)
271 #define INTMSK (0x01c00000+0x20000c)
272 #define LOCKTIME (0x01c00000+0x18000c)
273 #define PLLCON (0x01c00000+0x180000)
274 #define CLKCON (0x01c00000+0x180004)
275 #define WTCON (0x01c00000+0x130000)
277 /* disable watch dog */
283 * mask all IRQs by clearing all bits in the INTMRs
293 /* Set Clock Control Register */
300 #if CONFIG_S3C44B0_CLOCK_SPEED==66
301 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
302 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
303 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
305 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
317 /*************************************************/
318 /* interrupt vectors */
319 /*************************************************/
322 b undefined_instruction
330 /*************************************************/
332 undefined_instruction:
349 /* we *should* never reach this */