2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
27 tzic: tz-interrupt-controller@e0000000 {
28 compatible = "fsl,imx51-tzic", "fsl,tzic";
30 #interrupt-cells = <1>;
31 reg = <0xe0000000 0x4000>;
39 compatible = "fsl,imx-ckil", "fixed-clock";
40 clock-frequency = <32768>;
44 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>;
49 compatible = "fsl,imx-ckih2", "fixed-clock";
50 clock-frequency = <0>;
54 compatible = "fsl,imx-osc", "fixed-clock";
55 clock-frequency = <24000000>;
62 compatible = "simple-bus";
63 interrupt-parent = <&tzic>;
67 compatible = "fsl,ahb-bus", "simple-bus";
70 reg = <0x40000000 0x60000000>;
76 compatible = "fsl,imx-ipuv3";
77 reg = <0x5e000000 0x02000000>;
83 aips@70000000 { /* AIPS1 */
84 compatible = "fsl,aips-bus", "simple-bus";
87 reg = <0x70000000 0x10000000>;
91 compatible = "fsl,spba-bus", "simple-bus";
94 reg = <0x70000000 0x40000>;
97 esdhc@70004000 { /* ESDHC1 */
98 compatible = "fsl,imx51-esdhc";
99 reg = <0x70004000 0x4000>;
104 esdhc@70008000 { /* ESDHC2 */
105 compatible = "fsl,imx51-esdhc";
106 reg = <0x70008000 0x4000>;
111 uart3: serial@7000c000 {
112 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
113 reg = <0x7000c000 0x4000>;
118 ecspi@70010000 { /* ECSPI1 */
119 #address-cells = <1>;
121 compatible = "fsl,imx51-ecspi";
122 reg = <0x70010000 0x4000>;
128 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
129 reg = <0x70014000 0x4000>;
131 fsl,fifo-depth = <15>;
132 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
136 esdhc@70020000 { /* ESDHC3 */
137 compatible = "fsl,imx51-esdhc";
138 reg = <0x70020000 0x4000>;
143 esdhc@70024000 { /* ESDHC4 */
144 compatible = "fsl,imx51-esdhc";
145 reg = <0x70024000 0x4000>;
152 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
153 reg = <0x73f80000 0x0200>;
159 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
160 reg = <0x73f80200 0x0200>;
166 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
167 reg = <0x73f80400 0x0200>;
173 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
174 reg = <0x73f80600 0x0200>;
179 gpio1: gpio@73f84000 {
180 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
181 reg = <0x73f84000 0x4000>;
182 interrupts = <50 51>;
185 interrupt-controller;
186 #interrupt-cells = <2>;
189 gpio2: gpio@73f88000 {
190 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
191 reg = <0x73f88000 0x4000>;
192 interrupts = <52 53>;
195 interrupt-controller;
196 #interrupt-cells = <2>;
199 gpio3: gpio@73f8c000 {
200 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
201 reg = <0x73f8c000 0x4000>;
202 interrupts = <54 55>;
205 interrupt-controller;
206 #interrupt-cells = <2>;
209 gpio4: gpio@73f90000 {
210 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
211 reg = <0x73f90000 0x4000>;
212 interrupts = <56 57>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
220 compatible = "fsl,imx-keypad";
221 reg = <0x73f94000 0x4000>;
226 wdog@73f98000 { /* WDOG1 */
227 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
228 reg = <0x73f98000 0x4000>;
233 wdog@73f9c000 { /* WDOG2 */
234 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
235 reg = <0x73f9c000 0x4000>;
241 compatible = "fsl,imx51-iomuxc";
242 reg = <0x73fa8000 0x4000>;
245 pinctrl_audmux_1: audmuxgrp-1 {
247 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
248 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
249 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
250 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
256 pinctrl_fec_1: fecgrp-1 {
258 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
259 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
260 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
261 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
262 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
263 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
264 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
265 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
266 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
267 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
268 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
269 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
270 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
271 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
272 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
273 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
274 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
280 pinctrl_ecspi1_1: ecspi1grp-1 {
282 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
283 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
284 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
290 pinctrl_esdhc1_1: esdhc1grp-1 {
292 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
293 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
294 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
295 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
296 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
297 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
303 pinctrl_esdhc2_1: esdhc2grp-1 {
305 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
306 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
307 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
308 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
309 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
310 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
316 pinctrl_i2c2_1: i2c2grp-1 {
318 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
319 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
325 pinctrl_uart1_1: uart1grp-1 {
327 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
328 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
329 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
330 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
336 pinctrl_uart2_1: uart2grp-1 {
338 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
339 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
345 pinctrl_uart3_1: uart3grp-1 {
347 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
348 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
349 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
350 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
357 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
358 reg = <0x73fb4000 0x4000>;
364 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
365 reg = <0x73fb8000 0x4000>;
370 uart1: serial@73fbc000 {
371 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
372 reg = <0x73fbc000 0x4000>;
377 uart2: serial@73fc0000 {
378 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
379 reg = <0x73fc0000 0x4000>;
385 aips@80000000 { /* AIPS2 */
386 compatible = "fsl,aips-bus", "simple-bus";
387 #address-cells = <1>;
389 reg = <0x80000000 0x10000000>;
392 ecspi@83fac000 { /* ECSPI2 */
393 #address-cells = <1>;
395 compatible = "fsl,imx51-ecspi";
396 reg = <0x83fac000 0x4000>;
402 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
403 reg = <0x83fb0000 0x4000>;
405 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
409 #address-cells = <1>;
411 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
412 reg = <0x83fc0000 0x4000>;
417 i2c@83fc4000 { /* I2C2 */
418 #address-cells = <1>;
420 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
421 reg = <0x83fc4000 0x4000>;
426 i2c@83fc8000 { /* I2C1 */
427 #address-cells = <1>;
429 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
430 reg = <0x83fc8000 0x4000>;
436 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
437 reg = <0x83fcc000 0x4000>;
439 fsl,fifo-depth = <15>;
440 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
445 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
446 reg = <0x83fd0000 0x4000>;
448 ext-ports = <3 4 5 6>;
453 compatible = "fsl,imx51-nand";
454 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
460 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
461 reg = <0x83fe8000 0x4000>;
463 fsl,fifo-depth = <15>;
464 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
468 fec0: ethernet@83fec000 {
469 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
470 reg = <0x83fec000 0x4000>;