2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 /include/ "imx6qdl.dtsi"
18 compatible = "arm,cortex-a9";
20 next-level-cache = <&L2>;
26 clock-latency = <61036>; /* two CLK32 periods */
27 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
28 <&clks 17>, <&clks 170>;
29 clock-names = "arm", "pll2_pfd2_396m", "step",
30 "pll1_sw", "pll1_sys";
31 arm-supply = <®_arm>;
32 pu-supply = <®_pu>;
33 soc-supply = <®_soc>;
37 compatible = "arm,cortex-a9";
39 next-level-cache = <&L2>;
44 aips-bus@02000000 { /* AIPS1 */
46 ecspi5: ecspi@02018000 {
49 compatible = "fsl,iMX6DL-ecspi", "fsl,imx51-ecspi";
50 reg = <0x02018000 0x4000>;
51 interrupts = <0 35 0x04>;
52 clocks = <&clks 116>, <&clks 116>;
53 clock-names = "ipg", "per";
58 iomuxc: iomuxc@020e0000 {
59 compatible = "fsl,iMX6DL-iomuxc";
60 reg = <0x020e0000 0x4000>;
62 /* shared pinctrl settings */
64 pinctrl_audmux_1: audmux-1 {
66 18 0x80000000 /* MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
67 1586 0x80000000 /* MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
68 11 0x80000000 /* MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
69 3 0x80000000 /* MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
75 pinctrl_ecspi1_1: ecspi1grp-1 {
77 101 0x100b1 /* MX6DL_PAD_EIM_D17__ECSPI1_MISO */
78 109 0x100b1 /* MX6DL_PAD_EIM_D18__ECSPI1_MOSI */
79 94 0x100b1 /* MX6DL_PAD_EIM_D16__ECSPI1_SCLK */
85 pinctrl_enet_1: enetgrp-1 {
87 695 0x1b0b0 /* MX6DL_PAD_ENET_MDIO__ENET_MDIO */
88 756 0x1b0b0 /* MX6DL_PAD_ENET_MDC__ENET_MDC */
89 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
90 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
91 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
92 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
93 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
94 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
95 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
96 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
97 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
98 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
99 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
100 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
101 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
102 1033 0x4001b0a8 /* MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
106 pinctrl_enet_2: enetgrp-2 {
108 890 0x1b0b0 /* MX6DL_PAD_KEY_COL1__ENET_MDIO */
109 909 0x1b0b0 /* MX6DL_PAD_KEY_COL2__ENET_MDC */
110 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */
111 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */
112 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */
113 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */
114 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */
115 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
116 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */
117 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */
118 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */
119 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */
120 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */
121 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */
122 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
128 pinctrl_gpmi_nand_1: gpmi-nand-1 {
130 1328 0xb0b1 /* MX6DL_PAD_NANDF_CLE__RAWNAND_CLE */
131 1336 0xb0b1 /* MX6DL_PAD_NANDF_ALE__RAWNAND_ALE */
132 1344 0xb0b1 /* MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN */
133 1352 0xb000 /* MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 */
134 1360 0xb0b1 /* MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N */
135 1365 0xb0b1 /* MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N */
136 1371 0xb0b1 /* MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N */
137 1378 0xb0b1 /* MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N */
138 1387 0xb0b1 /* MX6DL_PAD_SD4_CMD__RAWNAND_RDN */
139 1393 0xb0b1 /* MX6DL_PAD_SD4_CLK__RAWNAND_WRN */
140 1397 0xb0b1 /* MX6DL_PAD_NANDF_D0__RAWNAND_D0 */
141 1405 0xb0b1 /* MX6DL_PAD_NANDF_D1__RAWNAND_D1 */
142 1413 0xb0b1 /* MX6DL_PAD_NANDF_D2__RAWNAND_D2 */
143 1421 0xb0b1 /* MX6DL_PAD_NANDF_D3__RAWNAND_D3 */
144 1429 0xb0b1 /* MX6DL_PAD_NANDF_D4__RAWNAND_D4 */
145 1437 0xb0b1 /* MX6DL_PAD_NANDF_D5__RAWNAND_D5 */
146 1445 0xb0b1 /* MX6DL_PAD_NANDF_D6__RAWNAND_D6 */
147 1453 0xb0b1 /* MX6DL_PAD_NANDF_D7__RAWNAND_D7 */
148 1463 0x00b1 /* MX6DL_PAD_SD4_DAT0__RAWNAND_DQS */
154 pinctrl_i2c1_1: i2c1grp-1 {
156 137 0x4001b8b1 /* MX6DL_PAD_EIM_D21__I2C1_SCL */
157 196 0x4001b8b1 /* MX6DL_PAD_EIM_D28__I2C1_SDA */
163 pinctrl_uart1_1: uart1grp-1 {
165 1140 0x1b0b1 /* MX6DL_PAD_CSI0_DAT10__UART1_TXD */
166 1148 0x1b0b1 /* MX6DL_PAD_CSI0_DAT11__UART1_RXD */
169 pinctrl_uart1_2: uart1-grp-2 {
171 120 0x1b0b1 /* MX6DL_PAD_EIM_D19__UART1_CTS */
172 128 0x1b0b1 /* MX6DL_PAD_EIM_D20__UART1_RTS */
176 pinctrl_uart1_3: uart1grp-3 {
178 1242 0x1b0b1 /* MX6DL_PAD_SD3_DAT7__UART1_TXD */
179 1250 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART1_RXD */
182 pinctrl_uart1_4: uart1-grp-4 {
184 1290 0x1b0b1 /* MX6DL_PAD_SD3_DAT0__UART1_CTS */
185 1298 0x1b0b1 /* MX6DL_PAD_SD3_DAT1__UART1_RTS */
191 pinctrl_uart2_1: uart2grp-1 {
193 183 0x1b0b1 /* MX6DL_PAD_EIM_D26__UART2_TXD */
194 191 0x1b0b1 /* MX6DL_PAD_EIM_D27__UART2_RXD */
197 pinctrl_uart2_2: uart2grp-2 {
199 199 0x1b0b1 /* MX6DL_PAD_EIM_D28__UART2_CTS */
200 206 0x1b0b1 /* MX6DL_PAD_EIM_D29__UART2_RTS */
204 pinctrl_uart2_3: uart2grp-3 {
206 1258 0x1b0b1 /* MX6DL_PAD_SD3_DAT5__UART2_TXD */
207 1266 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART2_RXD */
210 pinctrl_uart2_4: uart2grp-4 {
212 1274 0x1b0b1 /* MX6DL_PAD_SD3_CMD__UART2_CTS */
213 1282 0x1b0b1 /* MX6DL_PAD_SD3_CLK__UART2_RTS */
217 pinctrl_uart2_5: uart2grp-5 {
219 1518 0x1b0b1 /* MX6DL_PAD_SD4_DAT7__UART2_TXD */
220 1494 0x1b0b1 /* MX6DL_PAD_SD4_DAT4__UART2_RXD */
223 pinctrl_uart2_6: uart2grp-6 {
225 1510 0x1b0b1 /* MX6DL_PAD_SD4_DAT6__UART2_CTS */
226 1502 0x1b0b1 /* MX6DL_PAD_SD4_DAT5__UART2_RTS */
230 pinctrl_uart2_7: uart2grp-7 {
232 1019 0x1b0b1 /* MX6DL_PAD_GPIO_7__UART2_TXD */
233 1027 0x1b0b1 /* MX6DL_PAD_GPIO_8__UART2_RXD */
239 pinctrl_uart3_1: uart3grp-1 {
241 165 0x1b0b1 /* MX6DL_PAD_EIM_D24__UART3_TXD */
242 173 0x1b0b1 /* MX6DL_PAD_EIM_D25__UART3_RXD */
245 pinctrl_uart3_2: uart3grp-2 {
247 149 0x1b0b1 /* MX6DL_PAD_EIM_D23__UART3_CTS */
248 157 0x1b0b1 /* MX6DL_PAD_EIM_EB3__UART3_RTS */
252 pinctrl_uart3_3: uart3grp-3 {
254 1388 0x1b0b1 /* MX6DL_PAD_SD4_CMD__UART3_TXD */
255 1394 0x1b0b1 /* MX6DL_PAD_SD4_CLK__UART3_RXD */
258 pinctrl_uart3_4: uart3grp-4 {
260 1313 0x1b0b1 /* MX6DL_PAD_SD3_DAT3__UART3_CTS */
261 1321 0x1b0b1 /* MX6DL_PAD_SD3_RST__UART3_RTS */
265 pinctrl_uart3_5: uart3grp-5 {
267 214 0x1b0b1 /* MX6DL_PAD_EIM_D30__UART3_CTS */
268 222 0x1b0b1 /* MX6DL_PAD_EIM_D31__UART3_RTS */
274 pinctrl_uart4_1: uart4grp-1 {
276 877 0x1b0b1 /* MX6DL_PAD_KEY_COL0__UART4_TXD */
277 885 0x1b0b1 /* MX6DL_PAD_KEY_ROW0__UART4_RXD */
283 pinctrl_usbotg_1: usbotggrp-1 {
285 1592 0x17059 /* MX6DL_PAD_GPIO_1__ANATOP_USBOTG_ID */
291 pinctrl_usdhc1_1: usdhc1grp-1 {
293 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
294 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
295 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
296 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
297 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
298 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
299 1398 0x17059 /* MX6DL_PAD_NANDF_D0__USDHC1_DAT4 */
300 1406 0x17059 /* MX6DL_PAD_NANDF_D1__USDHC1_DAT5 */
301 1414 0x17059 /* MX6DL_PAD_NANDF_D2__USDHC1_DAT6 */
302 1422 0x17059 /* MX6DL_PAD_NANDF_D3__USDHC1_DAT7 */
306 pinctrl_usdhc1_2: usdhc1grp-2 {
308 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */
309 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */
310 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */
311 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */
312 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */
313 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */
319 pinctrl_usdhc2_1: usdhc2grp-1 {
321 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
322 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
323 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
324 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
325 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
326 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
327 1430 0x17059 /* MX6DL_PAD_NANDF_D4__USDHC2_DAT4 */
328 1438 0x17059 /* MX6DL_PAD_NANDF_D5__USDHC2_DAT5 */
329 1446 0x17059 /* MX6DL_PAD_NANDF_D6__USDHC2_DAT6 */
330 1454 0x17059 /* MX6DL_PAD_NANDF_D7__USDHC2_DAT7 */
334 pinctrl_usdhc2_2: usdhc2grp-2 {
336 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */
337 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */
338 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */
339 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */
340 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */
341 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */
347 pinctrl_usdhc3_1: usdhc3grp-1 {
349 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
350 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
351 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
352 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
353 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
354 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
355 1265 0x17059 /* MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 */
356 1257 0x17059 /* MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 */
357 1249 0x17059 /* MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 */
358 1241 0x17059 /* MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 */
362 pinctrl_usdhc3_2: usdhc3grp-2 {
364 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */
365 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */
366 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */
367 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */
368 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */
369 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */
375 pinctrl_usdhc4_1: usdhc4grp-1 {
377 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
378 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
379 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
380 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
381 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
382 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
383 1493 0x17059 /* MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 */
384 1501 0x17059 /* MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 */
385 1509 0x17059 /* MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 */
386 1517 0x17059 /* MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 */
390 pinctrl_usdhc4_2: usdhc4grp-2 {
392 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */
393 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */
394 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */
395 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */
396 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */
397 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */
406 compatible = "fsl,iMX6DL-ipu";
407 reg = <0x02800000 0x400000>;
408 interrupts = <0 8 0x4 0 7 0x4>;
409 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
410 clock-names = "bus", "di0", "di1";