3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
16 /* General purpose timers registers */
19 unsigned int prescaler;
21 unsigned int nouse[6];
25 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
27 /* General purpose timers bitfields */
28 #define GPTCR_SWR (1 << 15) /* Software reset */
29 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
30 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
31 #define GPTCR_TEN 1 /* Timer enable */
33 DECLARE_GLOBAL_DATA_PTR;
35 static inline unsigned long long tick_to_time(unsigned long long tick)
37 tick *= CONFIG_SYS_HZ;
38 do_div(tick, MXC_CLK32);
42 static inline unsigned long time_to_tick(unsigned long time)
44 unsigned long long ticks = (unsigned long long)time;
47 do_div(ticks, CONFIG_SYS_HZ);
51 static inline unsigned long long us_to_tick(unsigned long long usec)
53 usec = usec * MXC_CLK32 + 999999;
54 do_div(usec, 1000000);
63 /* setup GP Timer 1 */
64 __raw_writel(GPTCR_SWR, &cur_gpt->control);
66 /* We have no udelay by now */
67 for (i = 0; i < 100; i++)
68 __raw_writel(0, &cur_gpt->control);
70 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
72 /* Freerun Mode, PERCLK1 input */
73 i = __raw_readl(&cur_gpt->control);
74 __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
76 gd->arch.tbl = __raw_readl(&cur_gpt->counter);
79 gd->arch.timer_rate_hz = MXC_CLK32;
83 unsigned long long get_ticks(void)
85 ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
87 /* increment tbu if tbl has rolled over */
88 if (now < gd->arch.tbl)
91 return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
94 ulong get_timer_masked(void)
97 * get_ticks() returns a long long (64 bit), it wraps in
98 * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
99 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
100 * 5 * 10^6 days - long enough.
103 * LW: get_ticks() returns a long long with the top 32 bits always ZERO!
104 * Thus the calculation above is not true.
105 * A 64bit timer value would only make sense if it was
106 * consistently used throughout the code. Thus also the parameter
107 * to get_timer() and its return value would need to be 64bit wide!
109 return tick_to_time(get_ticks());
112 ulong get_timer(ulong base)
114 return tick_to_time(get_ticks() - time_to_tick(base));
117 /* delay x useconds AND preserve advance timstamp value */
118 void __udelay(unsigned long usec)
120 unsigned long start = __raw_readl(&cur_gpt->counter);
126 ticks = us_to_tick(usec);
130 while (__raw_readl(&cur_gpt->counter) - start < ticks)
131 /* loop till event */;
135 * This function is derived from PowerPC code (timebase clock frequency).
136 * On ARM it returns the number of timer ticks per second.
138 ulong get_tbclk(void)
140 return gd->arch.timer_rate_hz;