4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 #include <asm/arch/hardware.h>
20 #define BIT(x) (1 << (x))
21 #define CL_BIT(x) (0 << (x))
23 /* Timer register bits */
24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
25 #define TCLR_AR BIT(1) /* Auto reload */
26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
27 #define TCLR_PTV_SHIFT 2 /* Pre-scaler shift value */
28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
29 #define TCLR_CE BIT(6) /* compare mode enable */
30 #define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
31 #define TCLR_TCM BIT(8) /* edge detection of input pin*/
32 #define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
33 #define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
34 #define TCLR_CAPTMODE BIT(13) /* capture mode */
35 #define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
37 #define TCFG_RESET BIT(0) /* software reset */
38 #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
39 #define TCFG_IDLEMOD_SHIFT (2) /* power management */
41 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
42 #define TST_DEVICE 0x0
43 #define EMU_DEVICE 0x1
47 /* cpu-id for AM33XX and TI81XX family */
50 #define DEVICE_ID (CTRL_BASE + 0x0600)
51 #define DEVICE_ID_MASK 0x1FFF
53 /* MPU max frequencies */
54 #define AM335X_ZCZ_300 0x1FEF
55 #define AM335X_ZCZ_600 0x1FAF
56 #define AM335X_ZCZ_720 0x1F2F
57 #define AM335X_ZCZ_800 0x1E2F
58 #define AM335X_ZCZ_1000 0x1C2F
59 #define AM335X_ZCE_300 0x1FDF
60 #define AM335X_ZCE_600 0x1F9F
62 /* This gives the status of the boot mode pins on the evm */
63 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \
66 #define PRM_RSTCTRL_RESET 0x01
67 #define PRM_RSTST_WARM_RESET_MASK 0x232
71 * Using the prescaler, the OMAP watchdog could go for many
72 * months before firing. These limits work without scaling,
73 * with the 60 second default assumed by most tools and docs.
75 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
76 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
77 #define TIMER_MARGIN_MIN 1
79 #define PTV 0 /* prescale */
80 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
81 #define WDT_WWPS_PEND_WCLR BIT(0)
82 #define WDT_WWPS_PEND_WLDR BIT(2)
83 #define WDT_WWPS_PEND_WTGR BIT(3)
84 #define WDT_WWPS_PEND_WSPR BIT(4)
86 #define WDT_WCLR_PRE BIT(5)
87 #define WDT_WCLR_PTV_OFF 2
89 #ifndef __KERNEL_STRICT_NAMES
94 /* Encapsulating core pll registers */
96 unsigned int wkclkstctrl; /* offset 0x00 */
97 unsigned int wkctrlclkctrl; /* offset 0x04 */
98 unsigned int wkgpio0clkctrl; /* offset 0x08 */
99 unsigned int wkl4wkclkctrl; /* offset 0x0c */
100 unsigned int timer0clkctrl; /* offset 0x10 */
101 unsigned int resv2[3];
102 unsigned int idlestdpllmpu; /* offset 0x20 */
103 unsigned int resv3[2];
104 unsigned int clkseldpllmpu; /* offset 0x2c */
105 unsigned int resv4[1];
106 unsigned int idlestdpllddr; /* offset 0x34 */
107 unsigned int resv5[2];
108 unsigned int clkseldpllddr; /* offset 0x40 */
109 unsigned int autoidledplldisp; /* offset 0x44 */
110 unsigned int idlestdplldisp; /* offset 0x48 */
111 unsigned int resv6[2];
112 unsigned int clkseldplldisp; /* offset 0x54 */
113 unsigned int resv7[1];
114 unsigned int idlestdpllcore; /* offset 0x5c */
115 unsigned int resv8[2];
116 unsigned int clkseldpllcore; /* offset 0x68 */
117 unsigned int resv9[1];
118 unsigned int idlestdpllper; /* offset 0x70 */
119 unsigned int resv10[2];
120 unsigned int clkdcoldodpllper; /* offset 0x7c */
121 unsigned int divm4dpllcore; /* offset 0x80 */
122 unsigned int divm5dpllcore; /* offset 0x84 */
123 unsigned int clkmoddpllmpu; /* offset 0x88 */
124 unsigned int clkmoddpllper; /* offset 0x8c */
125 unsigned int clkmoddpllcore; /* offset 0x90 */
126 unsigned int clkmoddpllddr; /* offset 0x94 */
127 unsigned int clkmoddplldisp; /* offset 0x98 */
128 unsigned int clkseldpllper; /* offset 0x9c */
129 unsigned int divm2dpllddr; /* offset 0xA0 */
130 unsigned int divm2dplldisp; /* offset 0xA4 */
131 unsigned int divm2dpllmpu; /* offset 0xA8 */
132 unsigned int divm2dpllper; /* offset 0xAC */
133 unsigned int resv11[1];
134 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
135 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
136 unsigned int wkup_adctscctrl; /* offset 0xBC */
138 unsigned int timer1clkctrl; /* offset 0xC4 */
139 unsigned int resv13[4];
140 unsigned int divm6dpllcore; /* offset 0xD8 */
144 * Encapsulating peripheral functional clocks
148 unsigned int l4lsclkstctrl; /* offset 0x00 */
149 unsigned int l3sclkstctrl; /* offset 0x04 */
150 unsigned int l4fwclkstctrl; /* offset 0x08 */
151 unsigned int l3clkstctrl; /* offset 0x0c */
153 unsigned int cpgmac0clkctrl; /* offset 0x14 */
154 unsigned int lcdclkctrl; /* offset 0x18 */
155 unsigned int usb0clkctrl; /* offset 0x1c */
157 unsigned int tptc0clkctrl; /* offset 0x24 */
158 unsigned int emifclkctrl; /* offset 0x28 */
159 unsigned int ocmcramclkctrl; /* offset 0x2c */
160 unsigned int gpmcclkctrl; /* offset 0x30 */
161 unsigned int mcasp0clkctrl; /* offset 0x34 */
162 unsigned int uart5clkctrl; /* offset 0x38 */
163 unsigned int mmc0clkctrl; /* offset 0x3C */
164 unsigned int elmclkctrl; /* offset 0x40 */
165 unsigned int i2c2clkctrl; /* offset 0x44 */
166 unsigned int i2c1clkctrl; /* offset 0x48 */
167 unsigned int spi0clkctrl; /* offset 0x4C */
168 unsigned int spi1clkctrl; /* offset 0x50 */
169 unsigned int resv3[3];
170 unsigned int l4lsclkctrl; /* offset 0x60 */
171 unsigned int l4fwclkctrl; /* offset 0x64 */
172 unsigned int mcasp1clkctrl; /* offset 0x68 */
173 unsigned int uart1clkctrl; /* offset 0x6C */
174 unsigned int uart2clkctrl; /* offset 0x70 */
175 unsigned int uart3clkctrl; /* offset 0x74 */
176 unsigned int uart4clkctrl; /* offset 0x78 */
177 unsigned int timer7clkctrl; /* offset 0x7C */
178 unsigned int timer2clkctrl; /* offset 0x80 */
179 unsigned int timer3clkctrl; /* offset 0x84 */
180 unsigned int timer4clkctrl; /* offset 0x88 */
181 unsigned int resv4[8];
182 unsigned int gpio1clkctrl; /* offset 0xAC */
183 unsigned int gpio2clkctrl; /* offset 0xB0 */
184 unsigned int gpio3clkctrl; /* offset 0xB4 */
186 unsigned int tpccclkctrl; /* offset 0xBC */
187 unsigned int dcan0clkctrl; /* offset 0xC0 */
188 unsigned int dcan1clkctrl; /* offset 0xC4 */
190 unsigned int epwmss1clkctrl; /* offset 0xCC */
191 unsigned int emiffwclkctrl; /* offset 0xD0 */
192 unsigned int epwmss0clkctrl; /* offset 0xD4 */
193 unsigned int epwmss2clkctrl; /* offset 0xD8 */
194 unsigned int l3instrclkctrl; /* offset 0xDC */
195 unsigned int l3clkctrl; /* Offset 0xE0 */
196 unsigned int resv8[2];
197 unsigned int timer5clkctrl; /* offset 0xEC */
198 unsigned int timer6clkctrl; /* offset 0xF0 */
199 unsigned int mmc1clkctrl; /* offset 0xF4 */
200 unsigned int mmc2clkctrl; /* offset 0xF8 */
201 unsigned int resv9[8];
202 unsigned int l4hsclkstctrl; /* offset 0x11C */
203 unsigned int l4hsclkctrl; /* offset 0x120 */
204 unsigned int resv10[8];
205 unsigned int cpswclkstctrl; /* offset 0x144 */
206 unsigned int lcdcclkstctrl; /* offset 0x148 */
209 /* Encapsulating Display pll registers */
212 unsigned int clktimer7clk; /* offset 0x04 */
213 unsigned int clktimer2clk; /* offset 0x08 */
214 unsigned int clktimer3clk; /* offset 0x0C */
215 unsigned int clktimer4clk; /* offset 0x10 */
217 unsigned int clktimer5clk; /* offset 0x18 */
218 unsigned int clktimer6clk; /* offset 0x1C */
219 unsigned int resv3[2];
220 unsigned int clktimer1clk; /* offset 0x28 */
221 unsigned int resv4[2];
222 unsigned int clklcdcpixelclk; /* offset 0x34 */
225 struct prm_device_inst {
226 unsigned int prm_rstctrl;
227 unsigned int prm_rsttime;
228 unsigned int prm_rstst;
231 /* Encapsulating core pll registers */
233 unsigned int resv0[136];
234 unsigned int wkl4wkclkctrl; /* offset 0x220 */
235 unsigned int resv1[55];
236 unsigned int wkclkstctrl; /* offset 0x300 */
237 unsigned int resv2[15];
238 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
240 unsigned int wkup_uart0ctrl; /* offset 0x348 */
241 unsigned int resv4[5];
242 unsigned int wkctrlclkctrl; /* offset 0x360 */
244 unsigned int wkgpio0clkctrl; /* offset 0x368 */
246 unsigned int resv6[109];
247 unsigned int clkmoddpllcore; /* offset 0x520 */
248 unsigned int idlestdpllcore; /* offset 0x524 */
250 unsigned int clkseldpllcore; /* offset 0x52C */
251 unsigned int resv7[2];
252 unsigned int divm4dpllcore; /* offset 0x538 */
253 unsigned int divm5dpllcore; /* offset 0x53C */
254 unsigned int divm6dpllcore; /* offset 0x540 */
256 unsigned int resv8[7];
257 unsigned int clkmoddpllmpu; /* offset 0x560 */
258 unsigned int idlestdpllmpu; /* offset 0x564 */
260 unsigned int clkseldpllmpu; /* offset 0x56c */
261 unsigned int divm2dpllmpu; /* offset 0x570 */
263 unsigned int resv10[11];
264 unsigned int clkmoddpllddr; /* offset 0x5A0 */
265 unsigned int idlestdpllddr; /* offset 0x5A4 */
267 unsigned int clkseldpllddr; /* offset 0x5AC */
268 unsigned int divm2dpllddr; /* offset 0x5B0 */
270 unsigned int resv12[11];
271 unsigned int clkmoddpllper; /* offset 0x5E0 */
272 unsigned int idlestdpllper; /* offset 0x5E4 */
274 unsigned int clkseldpllper; /* offset 0x5EC */
275 unsigned int divm2dpllper; /* offset 0x5F0 */
276 unsigned int resv14[8];
277 unsigned int clkdcoldodpllper; /* offset 0x614 */
279 unsigned int resv15[2];
280 unsigned int clkmoddplldisp; /* offset 0x620 */
281 unsigned int resv16[2];
282 unsigned int clkseldplldisp; /* offset 0x62C */
283 unsigned int divm2dplldisp; /* offset 0x630 */
287 * Encapsulating peripheral functional clocks
291 unsigned int l3clkstctrl; /* offset 0x00 */
292 unsigned int resv0[7];
293 unsigned int l3clkctrl; /* Offset 0x20 */
294 unsigned int resv1[7];
295 unsigned int l3instrclkctrl; /* offset 0x40 */
296 unsigned int resv2[3];
297 unsigned int ocmcramclkctrl; /* offset 0x50 */
298 unsigned int resv3[9];
299 unsigned int tpccclkctrl; /* offset 0x78 */
301 unsigned int tptc0clkctrl; /* offset 0x80 */
303 unsigned int resv5[7];
304 unsigned int l4hsclkctrl; /* offset 0x0A0 */
306 unsigned int l4fwclkctrl; /* offset 0x0A8 */
307 unsigned int resv7[85];
308 unsigned int l3sclkstctrl; /* offset 0x200 */
309 unsigned int resv8[7];
310 unsigned int gpmcclkctrl; /* offset 0x220 */
311 unsigned int resv9[5];
312 unsigned int mcasp0clkctrl; /* offset 0x238 */
314 unsigned int mcasp1clkctrl; /* offset 0x240 */
316 unsigned int mmc2clkctrl; /* offset 0x248 */
317 unsigned int resv12[3];
318 unsigned int qspiclkctrl; /* offset 0x258 */
319 unsigned int resv121;
320 unsigned int usb0clkctrl; /* offset 0x260 */
321 unsigned int resv13[103];
322 unsigned int l4lsclkstctrl; /* offset 0x400 */
323 unsigned int resv14[7];
324 unsigned int l4lsclkctrl; /* offset 0x420 */
326 unsigned int dcan0clkctrl; /* offset 0x428 */
328 unsigned int dcan1clkctrl; /* offset 0x430 */
329 unsigned int resv17[13];
330 unsigned int elmclkctrl; /* offset 0x468 */
332 unsigned int resv18[3];
333 unsigned int gpio1clkctrl; /* offset 0x478 */
335 unsigned int gpio2clkctrl; /* offset 0x480 */
337 unsigned int gpio3clkctrl; /* offset 0x488 */
339 unsigned int gpio4clkctrl; /* offset 0x490 */
341 unsigned int gpio5clkctrl; /* offset 0x498 */
342 unsigned int resv21[3];
344 unsigned int i2c1clkctrl; /* offset 0x4A8 */
346 unsigned int i2c2clkctrl; /* offset 0x4B0 */
347 unsigned int resv23[3];
348 unsigned int mmc0clkctrl; /* offset 0x4C0 */
350 unsigned int mmc1clkctrl; /* offset 0x4C8 */
352 unsigned int resv25[13];
353 unsigned int spi0clkctrl; /* offset 0x500 */
355 unsigned int spi1clkctrl; /* offset 0x508 */
356 unsigned int resv27[9];
357 unsigned int timer2clkctrl; /* offset 0x530 */
359 unsigned int timer3clkctrl; /* offset 0x538 */
361 unsigned int timer4clkctrl; /* offset 0x540 */
362 unsigned int resv30[5];
363 unsigned int timer7clkctrl; /* offset 0x558 */
365 unsigned int resv31[9];
366 unsigned int uart1clkctrl; /* offset 0x580 */
368 unsigned int uart2clkctrl; /* offset 0x588 */
370 unsigned int uart3clkctrl; /* offset 0x590 */
372 unsigned int uart4clkctrl; /* offset 0x598 */
374 unsigned int uart5clkctrl; /* offset 0x5A0 */
375 unsigned int resv36[87];
377 unsigned int emifclkstctrl; /* offset 0x700 */
378 unsigned int resv361[7];
379 unsigned int emifclkctrl; /* offset 0x720 */
380 unsigned int resv37[3];
381 unsigned int emiffwclkctrl; /* offset 0x730 */
382 unsigned int resv371;
383 unsigned int otfaemifclkctrl; /* offset 0x738 */
384 unsigned int resv38[57];
385 unsigned int lcdclkctrl; /* offset 0x820 */
386 unsigned int resv39[183];
387 unsigned int cpswclkstctrl; /* offset 0xB00 */
388 unsigned int resv40[7];
389 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
392 struct cm_device_inst {
393 unsigned int cm_clkout1_ctrl;
394 unsigned int cm_dll_ctrl;
397 struct prm_device_inst {
398 unsigned int prm_rstctrl;
399 unsigned int prm_rstst;
404 unsigned int clktimer2clk; /* offset 0x04 */
405 unsigned int resv2[11];
406 unsigned int clkselmacclk; /* offset 0x34 */
408 #endif /* CONFIG_AM43XX */
410 /* Control Module RTC registers */
412 unsigned int rtcclkctrl; /* offset 0x0 */
413 unsigned int clkstctrl; /* offset 0x4 */
416 /* Watchdog timer registers */
418 unsigned int resv1[4];
419 unsigned int wdtwdsc; /* offset 0x010 */
420 unsigned int wdtwdst; /* offset 0x014 */
421 unsigned int wdtwisr; /* offset 0x018 */
422 unsigned int wdtwier; /* offset 0x01C */
423 unsigned int wdtwwer; /* offset 0x020 */
424 unsigned int wdtwclr; /* offset 0x024 */
425 unsigned int wdtwcrr; /* offset 0x028 */
426 unsigned int wdtwldr; /* offset 0x02C */
427 unsigned int wdtwtgr; /* offset 0x030 */
428 unsigned int wdtwwps; /* offset 0x034 */
429 unsigned int resv2[3];
430 unsigned int wdtwdly; /* offset 0x044 */
431 unsigned int wdtwspr; /* offset 0x048 */
432 unsigned int resv3[1];
433 unsigned int wdtwqeoi; /* offset 0x050 */
434 unsigned int wdtwqstar; /* offset 0x054 */
435 unsigned int wdtwqsta; /* offset 0x058 */
436 unsigned int wdtwqens; /* offset 0x05C */
437 unsigned int wdtwqenc; /* offset 0x060 */
438 unsigned int resv4[39];
439 unsigned int wdt_unfr; /* offset 0x100 */
442 /* Timer 32 bit registers */
444 unsigned int tidr; /* offset 0x00 */
445 unsigned char res1[12];
446 unsigned int tiocp_cfg; /* offset 0x10 */
447 unsigned char res2[12];
448 unsigned int tier; /* offset 0x20 */
449 unsigned int tistatr; /* offset 0x24 */
450 unsigned int tistat; /* offset 0x28 */
451 unsigned int tisr; /* offset 0x2c */
452 unsigned int tcicr; /* offset 0x30 */
453 unsigned int twer; /* offset 0x34 */
454 unsigned int tclr; /* offset 0x38 */
455 unsigned int tcrr; /* offset 0x3c */
456 unsigned int tldr; /* offset 0x40 */
457 unsigned int ttgr; /* offset 0x44 */
458 unsigned int twpc; /* offset 0x48 */
459 unsigned int tmar; /* offset 0x4c */
460 unsigned int tcar1; /* offset 0x50 */
461 unsigned int tsicr; /* offset 0x54 */
462 unsigned int tcar2; /* offset 0x58 */
467 unsigned int resv1[21];
468 unsigned int uartsyscfg; /* offset 0x54 */
469 unsigned int uartsyssts; /* offset 0x58 */
474 unsigned int vtp0ctrlreg;
477 /* Control Status Register */
479 unsigned int resv1[16];
480 unsigned int statusreg; /* ofset 0x40 */
481 unsigned int resv2[51];
482 unsigned int emif_sdram_config; /* offset 0x0110 */
483 unsigned int resv3[319];
484 unsigned int dev_attr;
487 /* AM33XX GPIO registers */
488 #define OMAP_GPIO_REVISION 0x0000
489 #define OMAP_GPIO_SYSCONFIG 0x0010
490 #define OMAP_GPIO_SYSSTATUS 0x0114
491 #define OMAP_GPIO_IRQSTATUS1 0x002c
492 #define OMAP_GPIO_IRQSTATUS2 0x0030
493 #define OMAP_GPIO_CTRL 0x0130
494 #define OMAP_GPIO_OE 0x0134
495 #define OMAP_GPIO_DATAIN 0x0138
496 #define OMAP_GPIO_DATAOUT 0x013c
497 #define OMAP_GPIO_LEVELDETECT0 0x0140
498 #define OMAP_GPIO_LEVELDETECT1 0x0144
499 #define OMAP_GPIO_RISINGDETECT 0x0148
500 #define OMAP_GPIO_FALLINGDETECT 0x014c
501 #define OMAP_GPIO_DEBOUNCE_EN 0x0150
502 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
503 #define OMAP_GPIO_CLEARDATAOUT 0x0190
504 #define OMAP_GPIO_SETDATAOUT 0x0194
506 /* Control Device Register */
508 /* Control Device Register */
509 #define MREQPRIO_0_SAB_INIT1_MASK 0xFFFFFF8F
510 #define MREQPRIO_0_SAB_INIT0_MASK 0xFFFFFFF8
511 #define MREQPRIO_1_DSS_MASK 0xFFFFFF8F
514 unsigned int deviceid; /* offset 0x00 */
515 unsigned int resv1[7];
516 unsigned int usb_ctrl0; /* offset 0x20 */
518 unsigned int usb_ctrl1; /* offset 0x28 */
520 unsigned int macid0l; /* offset 0x30 */
521 unsigned int macid0h; /* offset 0x34 */
522 unsigned int macid1l; /* offset 0x38 */
523 unsigned int macid1h; /* offset 0x3c */
524 unsigned int resv4[4];
525 unsigned int miisel; /* offset 0x50 */
526 unsigned int resv5[7];
527 unsigned int mreqprio_0; /* offset 0x70 */
528 unsigned int mreqprio_1; /* offset 0x74 */
529 unsigned int resv6[97];
530 unsigned int efuse_sma; /* offset 0x1FC */
533 /* Bandwidth Limiter Portion of the L3Fast Configuration Register */
534 #define BW_LIMITER_BW_FRAC_MASK 0xFFFFFFE0
535 #define BW_LIMITER_BW_INT_MASK 0xFFFFFFF0
536 #define BW_LIMITER_BW_WATERMARK_MASK 0xFFFFF800
538 struct l3f_cfg_bwlimiter {
540 u32 modena_init0_bw_fractional;
541 u32 modena_init0_bw_integer;
542 u32 modena_init0_watermark_0;
545 /* gmii_sel register defines */
546 #define GMII1_SEL_MII 0x0
547 #define GMII1_SEL_RMII 0x1
548 #define GMII1_SEL_RGMII 0x2
549 #define GMII2_SEL_MII 0x0
550 #define GMII2_SEL_RMII 0x4
551 #define GMII2_SEL_RGMII 0x8
552 #define RGMII1_IDMODE BIT(4)
553 #define RGMII2_IDMODE BIT(5)
554 #define RMII1_IO_CLK_EN BIT(6)
555 #define RMII2_IO_CLK_EN BIT(7)
557 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
558 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
559 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
560 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
561 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
566 unsigned int sysconfig;
567 unsigned int clkconfig;
568 unsigned int clkstatus;
570 #define ECAP_CLK_EN BIT(0)
571 #define ECAP_CLK_STOP_REQ BIT(1)
573 struct pwmss_ecap_regs {
580 unsigned int resv1[4];
581 unsigned short ecctl1;
582 unsigned short ecctl2;
585 /* Capture Control register 2 */
586 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
587 #define ECTRL2_MDSL_ECAP BIT(9)
588 #define ECTRL2_CTRSTP_FREERUN BIT(4)
589 #define ECTRL2_PLSL_LOW BIT(10)
590 #define ECTRL2_SYNC_EN BIT(5)
592 #define clk_get_rate(c,p) \
593 __clk_get_rate(readl(&(c)->clkseldpll##p), \
594 readl(&(c)->divm2dpll##p))
596 unsigned long __clk_get_rate(u32 m_n, u32 div_m2);
598 unsigned long mpu_clk_rate(void);
600 #endif /* __ASSEMBLY__ */
601 #endif /* __KERNEL_STRICT_NAMES */
603 /* Ethernet MAC ID from EFuse */
604 #define MAC_ID0_LO (CTRL_BASE + 0x630)
605 #define MAC_ID0_HI (CTRL_BASE + 0x634)
606 #define MAC_ID1_LO (CTRL_BASE + 0x638)
607 #define MAC_ID1_HI (CTRL_BASE + 0x63c)
608 #define MAC_MII_SEL (CTRL_BASE + 0x650)
610 #endif /* _AM33XX_CPU_H */