6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/hardware.h>
17 /* AM335X EMIF Register values */
18 #define VTP_CTRL_READY (0x1 << 5)
19 #define VTP_CTRL_ENABLE (0x1 << 6)
20 #define VTP_CTRL_FILTER_SHIFT 1
21 #define VTP_CTRL_FILTER_MASK (0x7 << VTP_CTRL_FILTER_SHIFT)
22 #define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK)
23 #define VTP_CTRL_START_EN (0x1 << 0)
24 #define PHY_DLL_LOCK_DIFF 0x0
25 #define DDR_CKE_CTRL_NORMAL 0x1
26 #define PHY_EN_DYN_PWRDN (0x1 << 20)
28 /* Micron MT47H128M16RT-25E */
29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
35 #define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
36 #define MT47H128M16RT25E_RATIO 0x80
37 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00
38 #define MT47H128M16RT25E_RD_DQS 0x12
39 #define MT47H128M16RT25E_WR_DQS 0x00
40 #define MT47H128M16RT25E_PHY_WRLVL 0x00
41 #define MT47H128M16RT25E_PHY_GATELVL 0x00
42 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
43 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
44 #define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
45 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
47 /* Micron MT41J128M16JT-125 */
48 #define MT41J128MJT125_EMIF_READ_LATENCY 0x06
49 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
50 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
51 #define MT41J128MJT125_EMIF_TIM3 0x501F830F
52 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
53 #define MT41J128MJT125_EMIF_SDREF 0x0000093B
54 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
55 #define MT41J128MJT125_DLL_LOCK_DIFF 0x1
56 #define MT41J128MJT125_RATIO 0x40
57 #define MT41J128MJT125_INVERT_CLKOUT 0x1
58 #define MT41J128MJT125_RD_DQS 0x3B
59 #define MT41J128MJT125_WR_DQS 0x85
60 #define MT41J128MJT125_PHY_WR_DATA 0xC1
61 #define MT41J128MJT125_PHY_FIFO_WE 0x100
62 #define MT41J128MJT125_IOCTRL_VALUE 0x18B
64 /* Micron MT41J256M8HX-15E */
65 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
66 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
67 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
68 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
69 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
70 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
71 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
72 #define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
73 #define MT41J256M8HX15E_RATIO 0x40
74 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1
75 #define MT41J256M8HX15E_RD_DQS 0x3B
76 #define MT41J256M8HX15E_WR_DQS 0x85
77 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1
78 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100
79 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
81 /* Micron MT41K256M16HA-125E */
82 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
83 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
84 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
85 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
86 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
87 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
88 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
89 #define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
90 #define MT41K256M16HA125E_RATIO 0x80
91 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
92 #define MT41K256M16HA125E_RD_DQS 0x38
93 #define MT41K256M16HA125E_WR_DQS 0x44
94 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
95 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
96 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
98 /* Micron MT41J512M8RH-125 on EVM v1.5 */
99 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
100 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
101 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
102 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
103 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
104 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B
105 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4
106 #define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
107 #define MT41J512M8RH125_RATIO 0x80
108 #define MT41J512M8RH125_INVERT_CLKOUT 0x0
109 #define MT41J512M8RH125_RD_DQS 0x3B
110 #define MT41J512M8RH125_WR_DQS 0x3C
111 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5
112 #define MT41J512M8RH125_PHY_WR_DATA 0x74
113 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
115 /* Samsung K4B2G1646E-BIH9 */
116 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x06
117 #define K4B2G1646EBIH9_EMIF_TIM1 0x0888A39B
118 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A04011A
119 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F820F
120 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C24AB2
121 #define K4B2G1646EBIH9_EMIF_SDREF 0x0000093B
122 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
123 #define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
124 #define K4B2G1646EBIH9_RATIO 0x40
125 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x1
126 #define K4B2G1646EBIH9_RD_DQS 0x3B
127 #define K4B2G1646EBIH9_WR_DQS 0x85
128 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x100
129 #define K4B2G1646EBIH9_PHY_WR_DATA 0xC1
130 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
135 void config_dmm(const struct dmm_lisa_map_regs *regs);
140 void config_sdram(const struct emif_regs *regs, int nr);
145 void set_sdram_timings(const struct emif_regs *regs, int nr);
150 void config_ddr_phy(const struct emif_regs *regs, int nr);
152 struct ddr_cmd_regs {
153 unsigned int resv0[7];
154 unsigned int cm0csratio; /* offset 0x01C */
155 unsigned int resv1[2];
156 unsigned int cm0dldiff; /* offset 0x028 */
157 unsigned int cm0iclkout; /* offset 0x02C */
158 unsigned int resv2[8];
159 unsigned int cm1csratio; /* offset 0x050 */
160 unsigned int resv3[2];
161 unsigned int cm1dldiff; /* offset 0x05C */
162 unsigned int cm1iclkout; /* offset 0x060 */
163 unsigned int resv4[8];
164 unsigned int cm2csratio; /* offset 0x084 */
165 unsigned int resv5[2];
166 unsigned int cm2dldiff; /* offset 0x090 */
167 unsigned int cm2iclkout; /* offset 0x094 */
168 unsigned int resv6[3];
171 struct ddr_data_regs {
172 unsigned int dt0rdsratio0; /* offset 0x0C8 */
173 unsigned int resv1[4];
174 unsigned int dt0wdsratio0; /* offset 0x0DC */
175 unsigned int resv2[4];
176 unsigned int dt0wiratio0; /* offset 0x0F0 */
178 unsigned int dt0wimode0; /* offset 0x0F8 */
179 unsigned int dt0giratio0; /* offset 0x0FC */
181 unsigned int dt0gimode0; /* offset 0x104 */
182 unsigned int dt0fwsratio0; /* offset 0x108 */
183 unsigned int resv5[4];
184 unsigned int dt0dqoffset; /* offset 0x11C */
185 unsigned int dt0wrsratio0; /* offset 0x120 */
186 unsigned int resv6[4];
187 unsigned int dt0rdelays0; /* offset 0x134 */
188 unsigned int dt0dldiff0; /* offset 0x138 */
189 unsigned int resv7[12];
193 * This structure represents the DDR registers on AM33XX devices.
194 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
195 * correspond to DATA1 registers defined here.
198 unsigned int resv0[7];
199 unsigned int cm0csratio; /* offset 0x01C */
200 unsigned int resv1[2];
201 unsigned int cm0dldiff; /* offset 0x028 */
202 unsigned int cm0iclkout; /* offset 0x02C */
203 unsigned int resv2[8];
204 unsigned int cm1csratio; /* offset 0x050 */
205 unsigned int resv3[2];
206 unsigned int cm1dldiff; /* offset 0x05C */
207 unsigned int cm1iclkout; /* offset 0x060 */
208 unsigned int resv4[8];
209 unsigned int cm2csratio; /* offset 0x084 */
210 unsigned int resv5[2];
211 unsigned int cm2dldiff; /* offset 0x090 */
212 unsigned int cm2iclkout; /* offset 0x094 */
213 unsigned int resv6[12];
214 unsigned int dt0rdsratio0; /* offset 0x0C8 */
215 unsigned int resv7[4];
216 unsigned int dt0wdsratio0; /* offset 0x0DC */
217 unsigned int resv8[4];
218 unsigned int dt0wiratio0; /* offset 0x0F0 */
220 unsigned int dt0wimode0; /* offset 0x0F8 */
221 unsigned int dt0giratio0; /* offset 0x0FC */
223 unsigned int dt0gimode0; /* offset 0x104 */
224 unsigned int dt0fwsratio0; /* offset 0x108 */
225 unsigned int resv11[4];
226 unsigned int dt0dqoffset; /* offset 0x11C */
227 unsigned int dt0wrsratio0; /* offset 0x120 */
228 unsigned int resv12[4];
229 unsigned int dt0rdelays0; /* offset 0x134 */
230 unsigned int dt0dldiff0; /* offset 0x138 */
234 * Encapsulates DDR CMD control registers.
237 unsigned long cmd0csratio;
238 unsigned long cmd0csforce;
239 unsigned long cmd0csdelay;
240 unsigned long cmd0dldiff;
241 unsigned long cmd0iclkout;
242 unsigned long cmd1csratio;
243 unsigned long cmd1csforce;
244 unsigned long cmd1csdelay;
245 unsigned long cmd1dldiff;
246 unsigned long cmd1iclkout;
247 unsigned long cmd2csratio;
248 unsigned long cmd2csforce;
249 unsigned long cmd2csdelay;
250 unsigned long cmd2dldiff;
251 unsigned long cmd2iclkout;
255 * Encapsulates DDR DATA registers.
258 unsigned long datardsratio0;
259 unsigned long datawdsratio0;
260 unsigned long datawiratio0;
261 unsigned long datagiratio0;
262 unsigned long datafwsratio0;
263 unsigned long datawrsratio0;
264 unsigned long datauserank0delay;
265 unsigned long datadldiff0;
269 * Configure DDR CMD control registers
271 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
274 * Configure DDR DATA registers
276 void config_ddr_data(const struct ddr_data *data, int nr);
279 * This structure represents the DDR io control on AM33XX devices.
281 struct ddr_cmdtctrl {
282 unsigned int cm0ioctl;
283 unsigned int cm1ioctl;
284 unsigned int cm2ioctl;
285 unsigned int resv2[12];
286 unsigned int dt0ioctl;
287 unsigned int dt1ioctl;
291 * Configure DDR io control registers
293 void config_io_ctrl(unsigned long val);
296 unsigned int ddrioctrl;
297 unsigned int resv1[325];
298 unsigned int ddrckectrl;
301 void config_ddr(unsigned int pll, unsigned int ioctrl,
302 const struct ddr_data *data, const struct cmd_control *ctrl,
303 const struct emif_regs *regs, int nr);
305 #endif /* _DDR_DEFS_H */