2 * (C) Copyright 2012 Samsung Electronics
3 * Donghwa Lee <dh09.lee@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_ARM_ARCH_SYSTEM_H_
9 #define __ASM_ARM_ARCH_SYSTEM_H_
12 struct exynos4_sysreg {
13 unsigned int res1[0x210 / 4];
14 unsigned int display_ctrl;
15 unsigned int display_ctrl2;
16 unsigned int camera_control;
17 unsigned int audio_endian;
18 unsigned int jtag_con;
21 struct exynos5_sysreg {
22 unsigned int res1[0x214 / 4];
23 unsigned int disp1blk_cfg;
24 unsigned int disp2blk_cfg;
25 unsigned int hdcp_e_fuse;
26 unsigned int gsclblk_cfg0;
27 unsigned int gsclblk_cfg1;
28 unsigned int reserved;
29 unsigned int ispblk_cfg;
30 unsigned int usb20phy_cfg;
31 unsigned int res2[0x29c / 4];
32 unsigned int mipi_dphy;
33 unsigned int dptx_dphy;
34 unsigned int phyclk_sel;
38 #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
40 #ifdef CONFIG_EXYNOS5420
42 * Data Synchronization Barrier acts as a special kind of memory barrier.
43 * No instruction in program order after this instruction executes until
44 * this instruction completes. This instruction completes when:
45 * - All explicit memory accesses before this instruction complete.
46 * - All Cache, Branch predictor and TLB maintenance operations before
47 * this instruction complete.
49 #define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
52 * This instruction causes an event to be signaled to all cores
53 * within a multiprocessor system. If SEV is implemented,
54 * WFE must also be implemented.
56 #define sev() __asm__ __volatile__ ("sev\n\t" : : );
58 * If the Event Register is not set, WFE suspends execution until
59 * one of the following events occurs:
60 * - an IRQ interrupt, unless masked by the CPSR I-bit
61 * - an FIQ interrupt, unless masked by the CPSR F-bit
62 * - an Imprecise Data abort, unless masked by the CPSR A-bit
63 * - a Debug Entry request, if Debug is enabled
64 * - an Event signaled by another processor using the SEV instruction.
65 * If the Event Register is set, WFE clears it and returns immediately.
66 * If WFE is implemented, SEV must also be implemented.
68 #define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
70 /* Move 0xd3 value to CPSR register to enable SVC mode */
71 #define svc32_mode_en() __asm__ __volatile__ \
72 ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
73 "msr cpsr_c, #0x13|0xC0\n\t" : : )
75 /* Set program counter with the given value */
76 #define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
78 /* Read Main Id register */
79 #define mrc_midr(x) __asm__ __volatile__ \
80 ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
82 /* Read Multiprocessor Affinity Register */
83 #define mrc_mpafr(x) __asm__ __volatile__ \
84 ("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
86 /* Read System Control Register */
87 #define mrc_sctlr(x) __asm__ __volatile__ \
88 ("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
90 /* Read Auxiliary Control Register */
91 #define mrc_auxr(x) __asm__ __volatile__ \
92 ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
94 /* Read L2 Control register */
95 #define mrc_l2_ctlr(x) __asm__ __volatile__ \
96 ("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
98 /* Read L2 Auxilliary Control register */
99 #define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
100 ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
102 /* Write System Control Register */
103 #define mcr_sctlr(x) __asm__ __volatile__ \
104 ("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
106 /* Write Auxiliary Control Register */
107 #define mcr_auxr(x) __asm__ __volatile__ \
108 ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
110 /* Invalidate all instruction caches to PoU */
111 #define mcr_icache(x) __asm__ __volatile__ \
112 ("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
114 /* Invalidate unified TLB */
115 #define mcr_tlb(x) __asm__ __volatile__ \
116 ("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
118 /* Write L2 Control register */
119 #define mcr_l2_ctlr(x) __asm__ __volatile__ \
120 ("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
122 /* Write L2 Auxilliary Control register */
123 #define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
124 ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
127 void set_usbhost_mode(unsigned int mode);
128 void set_system_display_ctrl(void);
129 int exynos_lcd_early_init(const void *blob);
131 #endif /* _EXYNOS4_SYSTEM_H */