2 * Copyright 2014, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
8 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
10 #include <fsl_ddrc_version.h>
12 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
13 /* Link Definitions */
14 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
16 #define CONFIG_SYS_IMMR 0x01000000
17 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
18 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
19 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
20 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
21 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
22 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
25 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
26 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
27 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
28 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
29 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
30 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
33 /* SP (Cortex-A5) related */
34 #define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
35 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
36 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
37 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
38 (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
39 #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
40 (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
42 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
43 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
44 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
45 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
47 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
48 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
49 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
50 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
52 /* TZ Protection Controller Definitions */
53 #define TZPC_BASE 0x02200000
54 #define TZPCR0SIZE_BASE (TZPC_BASE)
55 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
56 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
57 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
58 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
59 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
60 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
61 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
62 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
63 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
65 /* TZ Address Space Controller Definitions */
66 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
67 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
68 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
69 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
70 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
71 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
72 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
73 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
74 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
75 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
76 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
77 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
78 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
80 /* Generic Interrupt Controller Definitions */
81 #define GICD_BASE 0x06000000
82 #define GICR_BASE 0x06100000
85 #define SMMU_BASE 0x05000000 /* GR0 Base */
88 #define CONFIG_SYS_FSL_DDR_LE
89 #define CONFIG_VERY_BIG_RAM
90 #ifdef CONFIG_SYS_FSL_DDR4
91 #define CONFIG_SYS_FSL_DDRC_GEN4
93 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
95 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
96 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
97 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
98 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
101 #define CONFIG_SYS_FSL_IFC_LE
103 #ifdef CONFIG_LS2085A
104 #define CONFIG_MAX_CPUS 16
105 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
106 #define CONFIG_NUM_DDR_CONTROLLERS 3
107 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
109 #error SoC not defined
112 #ifdef CONFIG_LS2085A
113 #define CONFIG_SYS_FSL_ERRATUM_A008336
114 #define CONFIG_SYS_FSL_ERRATUM_A008514
117 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */