3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __ASM_ARCH_CLOCK_H
9 #define __ASM_ARCH_CLOCK_H
13 #ifdef CONFIG_SYS_MX6_HCLK
14 #define MXC_HCLK CONFIG_SYS_MX6_HCLK
16 #define MXC_HCLK 24000000
19 #ifdef CONFIG_SYS_MX6_CLK32
20 #define MXC_CLK32 CONFIG_SYS_MX6_CLK32
22 #define MXC_CLK32 32768
49 /* Source clock this clk depends on */
51 /* Secondary clock to enable/disable with this clock */
52 struct clk *secondary;
53 /* Current clock rate */
55 /* Reference count of clock enable/disable */
57 /* Register bit position for clock's enable/disable control. */
59 /* Register address for clock's enable/disable control. */
63 * Function ptr to recalculate the clock's rate based on parent
66 void (*recalc) (struct clk *);
68 * Function ptr to set the clock to a new rate. The rate must match a
69 * supported rate returned from round_rate. Leave blank if clock is not
72 int (*set_rate) (struct clk *, unsigned long);
74 * Function ptr to round the requested clock rate to the nearest
75 * supported rate that is less than or equal to the requested rate.
77 unsigned long (*round_rate) (struct clk *, unsigned long);
79 * Function ptr to enable the clock. Leave blank if clock can not
82 int (*enable) (struct clk *);
84 * Function ptr to disable the clock. Leave blank if clock can not
87 void (*disable) (struct clk *);
88 /* Function ptr to set the parent clock of the clock. */
89 int (*set_parent) (struct clk *, struct clk *);
92 u32 imx_get_uartclk(void);
93 u32 imx_get_fecclk(void);
94 unsigned int mxc_get_clock(enum mxc_clock clk);
95 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk);
96 void enable_ocotp_clk(unsigned char enable);
97 void enable_usboh3_clk(unsigned char enable);
98 int enable_sata_clock(void);
99 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
100 void ipu_clk_enable(void);
101 void ipu_clk_disable(void);
102 void ocotp_clk_enable(void);
103 void ocotp_clk_disable(void);
105 #endif /* __ASM_ARCH_CLOCK_H */