2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
66 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
67 #define MXC_CCM_CCR_COSC_EN (1 << 12)
69 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
71 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
73 #define MXC_CCM_CCR_OSCNT_OFFSET 0
75 /* Define the bits in register CCDR */
76 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
77 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
79 /* Define the bits in register CSR */
80 #define MXC_CCM_CSR_COSC_READY (1 << 5)
81 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
83 /* Define the bits in register CCSR */
84 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
85 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
86 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
87 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
88 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
89 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
90 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
91 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
92 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
93 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
94 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
96 /* Define the bits in register CACRR */
97 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
98 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
100 /* Define the bits in register CBCDR */
101 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
102 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
103 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
104 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
106 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
107 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
109 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
110 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
111 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
113 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
115 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
116 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
117 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
118 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
119 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
120 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
122 /* Define the bits in register CBCMR */
123 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
124 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
125 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
126 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
127 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
128 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
129 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
130 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
131 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
132 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
133 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
135 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
136 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
137 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
138 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
140 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
141 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
143 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
145 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
146 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
147 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
148 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
149 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
151 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
152 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
155 /* Define the bits in register CSCMR1 */
156 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
157 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
159 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
160 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
162 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
163 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
165 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
166 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
167 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
168 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
169 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
170 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
171 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
172 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
173 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
174 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
175 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
176 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
177 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
178 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
179 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
181 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
182 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
184 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
185 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
186 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
188 #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
189 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
191 /* Define the bits in register CSCMR2 */
193 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
194 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
196 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
197 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
198 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
199 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
201 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
202 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
203 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
204 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
206 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
207 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
210 /* Define the bits in register CSCDR1 */
212 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
213 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
215 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
216 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
217 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
218 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
219 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
220 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
221 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
222 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
224 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
225 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
226 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
227 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
230 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
231 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
233 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
235 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
238 #define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6
239 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
241 /* Define the bits in register CS1CDR */
242 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
243 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
244 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET)
245 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
246 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
247 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
248 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
249 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
250 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
251 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
252 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
253 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
255 /* Define the bits in register CS2CDR */
257 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
258 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
259 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
260 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
261 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
262 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET)
263 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
264 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
265 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET)
267 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
268 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
269 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
270 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
271 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
272 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
273 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
274 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
275 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
277 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
278 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
279 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
280 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
281 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
282 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
283 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
284 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
286 /* Define the bits in register CDCDR */
288 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
289 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
290 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
291 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET 28
293 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
294 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
295 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
296 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22
297 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
298 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
299 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
300 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
301 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
302 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
303 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
304 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
306 /* Define the bits in register CHSCCDR */
308 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
309 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
310 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
311 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
312 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET)
313 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
314 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET)
315 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
316 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_M4_PODF_OFFSET)
317 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
318 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET)
319 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
321 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
322 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
323 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
324 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
325 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
326 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
327 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
328 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
329 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
330 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
331 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
332 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
335 /* Define the bits in register CSCDR2 */
336 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
337 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
338 /* All IPU2_DI1 are LCDIF1 on MX6SX */
339 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
340 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
341 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
342 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
343 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
344 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
345 /* All IPU2_DI0 are LCDIF2 on MX6SX */
346 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
347 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
348 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
349 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
350 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
351 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
353 /* Define the bits in register CSCDR3 */
354 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
355 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
356 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
357 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
358 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
359 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
360 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
361 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
363 /* Define the bits in register CDHIPR */
364 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
365 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
367 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
369 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
370 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
371 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
372 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
374 /* Define the bits in register CLPCR */
375 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
376 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
378 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
379 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
380 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
382 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
383 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
385 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
386 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
388 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16)
389 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
390 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
391 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
392 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
393 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
394 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
395 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
397 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
398 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
399 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
401 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
402 #define MXC_CCM_CLPCR_LPM_OFFSET 0
404 /* Define the bits in register CISR */
405 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
407 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
409 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
410 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
411 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
412 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
413 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
414 #define MXC_CCM_CISR_COSC_READY (1 << 6)
415 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
417 /* Define the bits in register CIMR */
418 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
420 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
422 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
423 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
424 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
425 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19)
426 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
427 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
428 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
430 /* Define the bits in register CCOSR */
431 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
432 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
433 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
434 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
435 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
436 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
437 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
438 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
439 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
440 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
441 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
443 /* Define the bits in registers CGPR */
444 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
445 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
446 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
447 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
449 /* Define the bits in registers CCGRx */
450 #define MXC_CCM_CCGR_CG_MASK 3
452 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
453 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
454 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
455 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
456 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
457 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
458 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
459 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
460 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
461 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
462 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
463 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
464 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
465 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
466 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
467 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
468 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
469 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
470 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
471 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
472 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
473 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
474 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
475 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
476 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
477 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
478 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
479 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
481 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
482 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
484 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
485 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
488 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
489 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
490 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
491 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
492 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
493 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
494 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
495 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
496 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
497 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
499 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
500 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
502 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
503 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
504 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
505 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
506 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
507 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
509 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
510 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
512 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
513 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
514 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
515 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
517 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
518 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
520 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
521 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
523 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
524 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
525 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
526 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
530 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
531 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
533 #define MXC_CCM_CCGR2_CSI_OFFSET 2
534 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
537 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
538 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
540 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
541 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
542 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
543 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
544 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
545 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
546 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
547 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
548 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
549 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
550 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
551 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
552 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
553 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
554 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
555 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
556 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
557 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
559 #define MXC_CCM_CCGR2_LCD_OFFSET 28
560 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
561 #define MXC_CCM_CCGR2_PXP_OFFSET 30
562 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
564 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
565 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
566 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
567 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
571 #define MXC_CCM_CCGR3_M4_OFFSET 2
572 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
573 #define MXC_CCM_CCGR3_ENET_OFFSET 4
574 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
575 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
576 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
578 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
579 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
580 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
581 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
582 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
583 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
585 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
586 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
587 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
588 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
589 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
590 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
591 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
592 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
594 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
595 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
597 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
598 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
599 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
600 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
602 #define MXC_CCM_CCGR3_MLB_OFFSET 18
603 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
604 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
605 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
607 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
608 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
610 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
611 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
612 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
613 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
614 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
615 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
617 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
618 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
621 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
622 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
624 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
625 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
627 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
628 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
630 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
631 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
632 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
633 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
634 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
635 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
636 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
637 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
638 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
639 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
640 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
641 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
642 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
643 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
644 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
645 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
646 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
647 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
648 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
649 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
651 #define MXC_CCM_CCGR5_ROM_OFFSET 0
652 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
654 #define MXC_CCM_CCGR5_SATA_OFFSET 4
655 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
657 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
658 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
659 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
660 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
661 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
662 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
663 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
664 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
665 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
666 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
667 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
668 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
669 #define MXC_CCM_CCGR5_UART_OFFSET 24
670 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
671 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
672 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
674 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
675 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
676 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
677 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
680 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
681 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
682 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
683 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
684 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
685 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
686 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
687 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
688 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
689 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
690 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
691 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
692 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
693 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
695 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
696 #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
697 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
698 #define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
699 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
700 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
701 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
702 #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
703 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
704 #define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
705 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
706 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
707 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
708 #define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
709 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
710 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
711 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
712 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
713 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
714 #define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
715 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
716 #define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
717 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
719 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
720 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
721 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
722 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
723 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
724 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
725 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
726 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
727 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & \
728 BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
729 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M 0x0
730 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 0x1
731 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 0x2
732 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR 0x3
733 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
734 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
735 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
736 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
737 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
738 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
739 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
740 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
741 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
742 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
743 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
744 BM_ANADIG_PLL_ARM_DIV_SELECT)
746 #define BM_ANADIG_PLL_528_CTRL_LOCK (1 << 31)
747 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN (1 << 18)
748 #define BM_ANADIG_PLL_528_DITHER_ENABLE (1 << 17)
749 #define BM_ANADIG_PLL_528_CTRL_BYPASS (1 << 16)
750 #define BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC 14
751 #define BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
752 #define BF_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC(v) \
753 (((v) << BP_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC) & \
754 BM_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC)
755 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
756 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
757 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
758 #define BV_ANADIG_PLL_528_CTRL_BYPASS_CLK_SRC__XOR 0x3
759 #define BM_ANADIG_PLL_528_CTRL_ENABLE (1 << 13)
760 #define BM_ANADIG_PLL_528_CTRL_POWER (1 << 12)
761 #define BM_ANADIG_PLL_528_CTRL_HOLD_RING_OFF (1 << 11)
762 #define BM_ANADIG_PLL_528_CTRL_DOUBLE_CP (1 << 10)
763 #define BM_ANADIG_PLL_528_CTRL_HALF_CP (1 << 9)
764 #define BM_ANADIG_PLL_528_CTRL_DOUBLE_LF (1 << 8)
765 #define BM_ANADIG_PLL_528_CTRL_HALF_LF (1 << 7)
766 #define BM_ANADIG_PLL_528_CTRL_EN_USB_CLKS (1 << 6)
767 #define BP_ANADIG_PLL_528_CTRL_CONTROL0 2
768 #define BM_ANADIG_PLL_528_CTRL_CONTROL0 (0x7 << BP_ANADIG_PLL_528_CTRL_CONTROL0)
769 #define BF_ANADIG_PLL_528_CTRL_CONTROL0(v) \
770 (((v) << BP_ANADIG_PLL_528_CTRL_CONTROL0) & \
771 BM_ANADIG_PLL_528_CTRL_CONTROL0)
772 #define BP_ANADIG_PLL_528_CTRL_DIV_SELECT 0
773 #define BM_ANADIG_PLL_528_CTRL_DIV_SELECT (0x3 << BP_ANADIG_PLL_528_CTRL_DIV_SELECT)
774 #define BF_ANADIG_PLL_528_CTRL_DIV_SELECT(v) \
775 (((v) << BP_ANADIG_PLL_528_CTRL_DIV_SELECT) & \
776 BM_ANADIG_PLL_528_CTRL_DIV_SELECT)
778 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
779 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
780 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
781 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
782 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
783 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
784 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
785 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
786 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
787 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
788 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
789 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
790 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
791 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
792 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
793 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
794 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
795 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
796 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
797 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
798 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
799 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
800 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
801 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
802 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
803 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
804 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
805 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
806 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
808 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
809 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
810 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
811 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
812 BM_ANADIG_PLL_AUDIO_NUM_A)
814 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
815 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
816 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
817 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
818 BM_ANADIG_PLL_AUDIO_DENOM_B)
820 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
821 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
822 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
823 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
824 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
825 (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & \
826 BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
827 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
828 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
829 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
830 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
831 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
832 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
833 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
834 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
835 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
836 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
837 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
838 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
839 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
840 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
841 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
842 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
843 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
844 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
845 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
846 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
847 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
848 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
849 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
850 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
852 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
853 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
854 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
855 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
856 BM_ANADIG_PLL_VIDEO_NUM_A)
858 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
859 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
860 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
861 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
862 BM_ANADIG_PLL_VIDEO_DENOM_B)
864 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
865 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
866 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
867 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
868 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & \
869 BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
870 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
871 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
872 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
873 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & \
874 BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
875 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
876 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
877 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
878 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & \
879 BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
880 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
881 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
882 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
883 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & \
884 BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
885 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
886 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
887 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
888 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
889 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & \
890 BM_ANADIG_PLL_MLB_PHASE_SEL)
891 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
893 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
894 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
895 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
896 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
897 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
898 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
899 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
900 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
901 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
902 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
903 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
904 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
905 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
906 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
907 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
908 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
909 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
910 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
911 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
912 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
913 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
914 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
915 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
916 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
917 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
918 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
919 BM_ANADIG_PLL_ENET_DIV_SELECT)
921 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
922 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
923 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
924 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
925 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
926 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
927 BM_ANADIG_PFD_480_PFD3_FRAC)
929 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
930 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
931 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
932 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & \
933 BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
934 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
935 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
936 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
937 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
938 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & \
939 BM_ANADIG_ANA_MISC0_ANAMUX)
940 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
941 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
942 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
943 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
944 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & \
945 BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
946 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
947 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
948 #define BP_ANADIG_ANA_MISC0_OSC_I 14
949 #define BM_ANADIG_ANA_MISC0_OSC_I (0x3 << BP_ANADIG_ANA_MISC0_OSC_I)
950 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
951 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & \
952 BM_ANADIG_ANA_MISC0_OSC_I)
953 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
954 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
955 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
956 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST (0x3 << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
957 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
958 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & \
959 BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
960 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
961 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
962 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
963 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
964 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) & \
965 BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
966 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
967 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
968 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
969 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
971 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
972 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
973 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO (1 << 29)
974 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
975 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
976 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
977 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
978 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
979 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL (0x1f << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
980 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
981 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & \
982 BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
983 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
984 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL (0x1F << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
985 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
986 (((v) << BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) & \
987 BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
989 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
990 #define BM_ANADIG_ANA_MISC2_CONTROL3 (0x3 << BP_ANADIG_ANA_MISC2_CONTROL3)
991 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
992 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & \
993 BM_ANADIG_ANA_MISC2_CONTROL3)
994 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
995 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME)
996 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
997 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & \
998 BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
999 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
1000 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1001 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
1002 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & \
1003 BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1004 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
1005 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME (0x3 << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1006 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
1007 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & \
1008 BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1009 #define BM_ANADIG_ANA_MISC2_CONTROL2 (1 << 23)
1010 #define BM_ANADIG_ANA_MISC2_REG2_OK (1 << 22)
1011 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
1012 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
1013 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
1014 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1015 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
1016 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & \
1017 BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1018 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
1019 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
1020 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
1021 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
1022 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
1023 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET
1024 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
1025 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & \
1026 BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1027 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
1028 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
1029 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
1030 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
1031 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
1032 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1033 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
1034 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & \
1035 BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1037 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
1038 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1039 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
1040 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & \
1041 BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1042 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
1043 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1044 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
1045 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & \
1046 BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1047 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
1048 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
1049 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1050 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
1051 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & \
1052 BM_ANADIG_TEMPSENSE0_VBGADJ)
1053 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
1054 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
1055 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
1057 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
1058 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1059 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
1060 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & \
1061 BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1063 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
1064 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
1065 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
1066 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
1067 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
1068 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
1069 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
1070 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
1071 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
1072 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
1073 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
1074 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
1076 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
1077 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
1078 #define MXC_CCM_CCGR6_VADC_OFFSET 20
1079 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
1080 #define MXC_CCM_CCGR6_GIS_OFFSET 22
1081 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
1082 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
1083 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
1084 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
1085 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
1086 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
1087 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
1088 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
1089 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
1091 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
1092 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
1095 #define BM_ANADIG_USB_PLL_480_CTRL_LOCK (1 << 31)
1096 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS (1 << 16)
1097 #define BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC 14
1098 #define BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
1099 #define BF_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
1100 (((v) << BP_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC) & \
1101 BM_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC)
1102 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
1103 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
1104 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
1105 #define BV_ANADIG_USB_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
1106 #define BM_ANADIG_USB_PLL_480_CTRL_ENABLE (1 << 13)
1107 #define BM_ANADIG_USB_PLL_480_CTRL_POWER (1 << 12)
1108 #define BM_ANADIG_USB_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
1109 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_CP (1 << 10)
1110 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_CP (1 << 9)
1111 #define BM_ANADIG_USB_PLL_480_CTRL_DOUBLE_LF (1 << 8)
1112 #define BM_ANADIG_USB_PLL_480_CTRL_HALF_LF (1 << 7)
1113 #define BM_ANADIG_USB_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
1114 #define BP_ANADIG_USB_PLL_480_CTRL_CONTROL0 2
1115 #define BM_ANADIG_USB_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0)
1116 #define BF_ANADIG_USB_PLL_480_CTRL_CONTROL0(v) \
1117 (((v) << BP_ANADIG_USB_PLL_480_CTRL_CONTROL0) & \
1118 BM_ANADIG_USB_PLL_480_CTRL_CONTROL0)
1119 #define BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT 0
1120 #define BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
1121 #define BF_ANADIG_USB_PLL_480_CTRL_DIV_SELECT(v) \
1122 (((v) << BP_ANADIG_USB_PLL_480_CTRL_DIV_SELECT) & \
1123 BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT)
1125 #define BM_ANADIG_PLL_528_LOCK (1 << 31)
1126 #define BM_ANADIG_PLL_528_PLL_SEL (1 << 19)
1127 #define BM_ANADIG_PLL_528_LVDS_24MHZ_SEL (1 << 18)
1128 #define BM_ANADIG_PLL_528_LVDS_SEL (1 << 17)
1129 #define BM_ANADIG_PLL_528_BYPASS (1 << 16)
1130 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
1131 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_528_BYPASS_CLK_SRC)
1132 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
1133 (((v) << BP_ANADIG_PLL_528_BYPASS_CLK_SRC) & \
1134 BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
1135 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
1136 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
1137 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
1138 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
1139 #define BM_ANADIG_PLL_528_ENABLE (1 << 13)
1140 #define BM_ANADIG_PLL_528_POWERDOWN (1 << 12)
1141 #define BM_ANADIG_PLL_528_HOLD_RING_OFF (1 << 11)
1142 #define BM_ANADIG_PLL_528_DOUBLE_CP (1 << 10)
1143 #define BM_ANADIG_PLL_528_HALF_CP (1 << 9)
1144 #define BM_ANADIG_PLL_528_DOUBLE_LF (1 << 8)
1145 #define BM_ANADIG_PLL_528_HALF_LF (1 << 7)
1146 #define BP_ANADIG_PLL_528_DIV_SELECT 0
1147 #define BM_ANADIG_PLL_528_DIV_SELECT (0x7F << BP_ANADIG_PLL_528_DIV_SELECT)
1148 #define BF_ANADIG_PLL_528_DIV_SELECT(v) \
1149 (((v) << BP_ANADIG_PLL_528_DIV_SELECT) & \
1150 BM_ANADIG_PLL_528_DIV_SELECT)
1152 #define BP_ANADIG_PLL_528_SS_STOP 16
1153 #define BM_ANADIG_PLL_528_SS_STOP (0xFFFF << BP_ANADIG_PLL_528_SS_STOP)
1154 #define BF_ANADIG_PLL_528_SS_STOP(v) \
1155 (((v) << BP_ANADIG_PLL_528_SS_STOP) & \
1156 BM_ANADIG_PLL_528_SS_STOP)
1157 #define BM_ANADIG_PLL_528_SS_ENABLE (1 << 15)
1158 #define BP_ANADIG_PLL_528_SS_STEP 0
1159 #define BM_ANADIG_PLL_528_SS_STEP (0x7FFF << BP_ANADIG_PLL_528_SS_STEP)
1160 #define BF_ANADIG_PLL_528_SS_STEP(v) \
1161 (((v) << BP_ANADIG_PLL_528_SS_STEP) & \
1162 BM_ANADIG_PLL_528_SS_STEP)
1164 #define BP_ANADIG_PLL_528_NUM_A 0
1165 #define BM_ANADIG_PLL_528_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_528_NUM_A)
1166 #define BF_ANADIG_PLL_528_NUM_A(v) \
1167 (((v) << BP_ANADIG_PLL_528_NUM_A) & \
1168 BM_ANADIG_PLL_528_NUM_A)
1170 #define BP_ANADIG_PLL_528_DENOM_B 0
1171 #define BM_ANADIG_PLL_528_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_528_DENOM_B)
1172 #define BF_ANADIG_PLL_528_DENOM_B(v) \
1173 (((v) << BP_ANADIG_PLL_528_DENOM_B) & \
1174 BM_ANADIG_PLL_528_DENOM_B)
1176 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
1177 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
1178 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
1179 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1180 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
1181 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & \
1182 BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
1183 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
1184 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
1185 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
1186 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
1187 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1188 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
1189 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & \
1190 BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
1191 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
1192 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
1193 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
1194 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
1195 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
1196 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
1197 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
1198 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
1199 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
1200 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
1201 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
1202 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
1203 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
1204 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
1205 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & \
1206 BM_ANADIG_PLL_AUDIO_DIV_SELECT)
1208 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
1209 #define BM_ANADIG_PLL_AUDIO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_NUM_A)
1210 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
1211 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & \
1212 BM_ANADIG_PLL_AUDIO_NUM_A)
1214 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
1215 #define BM_ANADIG_PLL_AUDIO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_AUDIO_DENOM_B)
1216 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
1217 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & \
1218 BM_ANADIG_PLL_AUDIO_DENOM_B)
1220 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
1221 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
1222 #define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
1223 #define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1224 #define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
1225 (((v) << BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT) & \
1226 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
1227 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
1228 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
1229 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
1230 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
1231 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1232 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
1233 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & \
1234 BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
1235 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
1236 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
1237 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
1238 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
1239 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
1240 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
1241 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
1242 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
1243 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
1244 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
1245 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
1246 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
1247 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
1248 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
1249 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & \
1250 BM_ANADIG_PLL_VIDEO_DIV_SELECT)
1252 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
1253 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
1254 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
1255 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & \
1256 BM_ANADIG_PLL_VIDEO_NUM_A)
1258 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
1259 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
1260 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
1261 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & \
1262 BM_ANADIG_PLL_VIDEO_DENOM_B)
1264 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
1265 #define BM_ANADIG_PLL_ENET_REF_25M_ENABLE (1 << 21)
1266 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
1267 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
1268 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
1269 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
1270 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
1271 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
1272 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1273 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
1274 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & \
1275 BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
1276 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
1277 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
1278 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
1279 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
1280 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
1281 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
1282 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
1283 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
1284 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
1285 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
1286 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
1287 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1288 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
1289 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1290 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & \
1291 BM_ANADIG_PLL_ENET_DIV_SELECT)
1293 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
1294 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
1295 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1296 #define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC)
1297 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1298 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & \
1299 BM_ANADIG_PFD_480_PFD3_FRAC)
1300 #define BM_ANADIG_PFD_480_PFD2_CLKGATE (1 << 23)
1301 #define BM_ANADIG_PFD_480_PFD2_STABLE (1 << 22)
1302 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1303 #define BM_ANADIG_PFD_480_PFD2_FRAC (0x3F << BP_ANADIG_PFD_480_PFD2_FRAC)
1304 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1305 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & \
1306 BM_ANADIG_PFD_480_PFD2_FRAC)
1307 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
1308 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
1309 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1310 #define BM_ANADIG_PFD_480_PFD1_FRAC (0x3F << BP_ANADIG_PFD_480_PFD1_FRAC)
1311 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1312 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & \
1313 BM_ANADIG_PFD_480_PFD1_FRAC)
1314 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
1315 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
1316 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1317 #define BM_ANADIG_PFD_480_PFD0_FRAC (0x3F << BP_ANADIG_PFD_480_PFD0_FRAC)
1318 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1319 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & \
1320 BM_ANADIG_PFD_480_PFD0_FRAC)
1322 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
1323 #define BM_ANADIG_PFD_528_PFD3_STABLE (1 << 30)
1324 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1325 #define BM_ANADIG_PFD_528_PFD3_FRAC (0x3F << BP_ANADIG_PFD_528_PFD3_FRAC)
1326 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1327 (((v) << BP_ANADIG_PFD_528_PFD3_FRAC) & \
1328 BM_ANADIG_PFD_528_PFD3_FRAC)
1329 #define BM_ANADIG_PFD_528_PFD2_CLKGATE (1 << 23)
1330 #define BM_ANADIG_PFD_528_PFD2_STABLE (1 << 22)
1331 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1332 #define BM_ANADIG_PFD_528_PFD2_FRAC (0x3F << BP_ANADIG_PFD_528_PFD2_FRAC)
1333 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1334 (((v) << BP_ANADIG_PFD_528_PFD2_FRAC) & \
1335 BM_ANADIG_PFD_528_PFD2_FRAC)
1336 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
1337 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
1338 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1339 #define BM_ANADIG_PFD_528_PFD1_FRAC (0x3F << BP_ANADIG_PFD_528_PFD1_FRAC)
1340 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1341 (((v) << BP_ANADIG_PFD_528_PFD1_FRAC) & \
1342 BM_ANADIG_PFD_528_PFD1_FRAC)
1343 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
1344 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
1345 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1346 #define BM_ANADIG_PFD_528_PFD0_FRAC (0x3F << BP_ANADIG_PFD_528_PFD0_FRAC)
1347 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1348 (((v) << BP_ANADIG_PFD_528_PFD0_FRAC) & \
1349 BM_ANADIG_PFD_528_PFD0_FRAC)
1351 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */