3 * Texas Instruments, <www.ti.com>
6 * Aneesh V <aneesh@ti.com>
7 * Sricharan R <r.sricharan@ti.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
32 #include <asm/types.h>
33 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
36 * L4 Peripherals - L4 Wakeup and L4 Core now
38 #define OMAP54XX_L4_CORE_BASE 0x4A000000
39 #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
40 #define OMAP54XX_L4_PER_BASE 0x48000000
42 #define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000
43 #define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF
44 #define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START
45 #define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END
48 #define CONTROL_ID_CODE 0x4A002204
51 #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
52 #define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
53 #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
54 #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
55 #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
58 #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
59 #define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
60 #define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
62 /* General Purpose Timers */
63 #define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
64 #define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
65 #define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
67 /* Watchdog Timer2 - MPU watchdog */
68 #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
71 #define OMAP54XX_GPMC_BASE 0x50000000
74 * Hardware Register Details
78 #define WD_UNLOCK1 0xAAAA
79 #define WD_UNLOCK2 0x5555
82 #define TCLR_ST (0x1 << 0)
83 #define TCLR_AR (0x1 << 1)
84 #define TCLR_PRE (0x1 << 5)
87 #define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
88 #define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
89 #define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
90 #define CONTROL_EFUSE_2_OVERRIDE 0x00084000
93 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
94 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
95 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
96 #define LPDDR2IO_GR10_WD_MASK (3 << 17)
97 #define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
100 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
102 #define SDCARD_PWRDNZ (1 << 26)
103 #define SDCARD_BIAS_HIZ_MODE (1 << 25)
104 #define SDCARD_BIAS_PWRDNZ (1 << 22)
105 #define SDCARD_PBIASLITE_VMODE (1 << 21)
110 unsigned char res[0x10];
111 unsigned int s32k_cr; /* 0x10 */
114 #define DEVICE_TYPE_SHIFT 0x6
115 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
116 #define DEVICE_GP 0x3
118 /* Output impedance control */
119 #define ds_120_ohm 0x0
120 #define ds_60_ohm 0x1
121 #define ds_45_ohm 0x2
122 #define ds_30_ohm 0x3
125 /* Slew rate control */
127 #define sc_medium 0x1
132 /* Target capacitance control */
133 #define lb_5_12_pf 0x0
134 #define lb_12_25_pf 0x1
135 #define lb_25_50_pf 0x2
136 #define lb_50_80_pf 0x3
139 #define usb_i_mask 0x7
141 #define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
142 #define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
143 #define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
144 #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
145 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
147 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
148 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
149 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
150 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
151 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
153 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
154 #define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465
155 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
156 #define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8
157 #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
159 #define EFUSE_1 0x45145100
160 #define EFUSE_2 0x45145100
161 #define EFUSE_3 0x45145100
162 #define EFUSE_4 0x45145100
163 #endif /* __ASSEMBLY__ */
166 * Non-secure SRAM Addresses
167 * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
168 * at 0x40304000(EMU base) so that our code works for both EMU and GP
170 #define NON_SECURE_SRAM_START 0x40300000
171 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
172 /* base address for indirect vectors (internal boot mode) */
173 #define SRAM_ROM_VECT_BASE 0x4031F000
175 /* CONTROL_SRCOMP_XXX_SIDE */
176 #define OVERRIDE_XS_SHIFT 30
177 #define OVERRIDE_XS_MASK (1 << 30)
178 #define SRCODE_READ_XS_SHIFT 12
179 #define SRCODE_READ_XS_MASK (0xff << 12)
180 #define PWRDWN_XS_SHIFT 11
181 #define PWRDWN_XS_MASK (1 << 11)
182 #define DIVIDE_FACTOR_XS_SHIFT 4
183 #define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
184 #define MULTIPLY_FACTOR_XS_SHIFT 1
185 #define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
186 #define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
187 #define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
190 #define OMAP_ABB_SETTLING_TIME 50
191 #define OMAP_ABB_CLOCK_CYCLES 16
193 /* ABB tranxdone mask */
194 #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
196 /* ABB efuse masks */
197 #define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
198 #define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29)
199 #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
200 #define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
203 struct srcomp_params {
215 u32 ctrl_emif_sdram_config_ext;
217 #endif /* __ASSEMBLY__ */