2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
10 struct rk3399_grf_regs {
15 u32 usb3_perf_rd_max_latency_num;
16 u32 usb3_perf_rd_latency_samp_num;
17 u32 usb3_perf_rd_latency_acc_num;
18 u32 usb3_perf_rd_axi_total_byte;
19 u32 usb3_perf_wr_axi_total_byte;
20 u32 usb3_perf_working_cnt;
28 u32 usb3otg0_status_lat0;
29 u32 usb3otg0_status_lat1;
30 u32 usb3otg0_status_cb;
32 u32 usb3otg1_status_lat0;
33 u32 usb3otg1_status_lat1;
34 u32 usb3ogt1_status_cb;
39 u32 pcie_perf_rd_max_latency_num;
40 u32 pcie_perf_rd_latency_samp_num;
41 u32 pcie_perf_rd_laterncy_acc_num;
42 u32 pcie_perf_rd_axi_total_byte;
43 u32 pcie_perf_wr_axi_total_byte;
44 u32 pcie_perf_working_cnt;
55 u32 grf_usbhost0_status;
56 u32 grf_usbhost1_Status;
64 u32 reserved13[0x72f];
74 u32 reserved15[0xf65];
80 u32 a53_perf_rd_mon_st;
81 u32 a53_perf_rd_mon_end;
82 u32 a53_perf_wr_mon_st;
83 u32 a53_perf_wr_mon_end;
84 u32 a53_perf_rd_max_latency_num;
85 u32 a53_perf_rd_latency_samp_num;
86 u32 a53_perf_rd_laterncy_acc_num;
87 u32 a53_perf_rd_axi_total_byte;
88 u32 a53_perf_wr_axi_total_byte;
89 u32 a53_perf_working_cnt;
90 u32 a53_perf_int_status;
93 u32 a72_perf_rd_mon_st;
94 u32 a72_perf_rd_mon_end;
95 u32 a72_perf_wr_mon_st;
96 u32 a72_perf_wr_mon_end;
97 u32 a72_perf_rd_max_latency_num;
98 u32 a72_perf_rd_latency_samp_num;
99 u32 a72_perf_rd_laterncy_acc_num;
100 u32 a72_perf_rd_axi_total_byte;
101 u32 a72_perf_wr_axi_total_byte;
102 u32 a72_perf_working_cnt;
103 u32 a72_perf_int_status;
104 u32 reserved19[0x7f6];
107 u32 reserved20[0x779];
142 u32 iomux_edp_hotplug;
152 u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
155 u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
166 u32 reserved26[0x1e];
168 u32 reserved27[0x32];
173 u32 reserved28[0xac];
178 u32 reserved29[0x6c];
180 u32 reserved30[0x1f];
182 u32 reserved31[0x1df];
183 u32 emmccore_con[12];
185 u32 emmccore_status[4];
186 u32 reserved33[0x1cc];
191 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
193 struct rk3399_pmugrf_regs {
254 u32 reserved17[0x24];
260 u32 reserved18[0x2b];
266 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
268 struct rk3399_pmusgrf_regs {
270 u32 reserved[0x1fe5];
288 u32 reserved5[0xfaf];
301 u32 reserved10[0x771];
311 u32 reserved12[0xdd];
319 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
321 #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */