arch/arm/include/asm/arch-tegra20/display.h

   1 /*
   2  *  (C) Copyright 2010
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __ASM_ARCH_TEGRA_DISPLAY_H
   9 #define __ASM_ARCH_TEGRA_DISPLAY_H
  10
  11 #include <asm/arch-tegra/dc.h>
  12 #include <fdtdec.h>
  13 #include <asm/gpio.h>
  14
  15 /* This holds information about a window which can be displayed */
  16 struct disp_ctl_win {
  17         enum win_color_depth_id fmt;    /* Color depth/format */
  18         unsigned        bpp;            /* Bits per pixel */
  19         phys_addr_t     phys_addr;      /* Physical address in memory */
  20         unsigned        x;              /* Horizontal address offset (bytes) */
  21         unsigned        y;              /* Veritical address offset (bytes) */
  22         unsigned        w;              /* Width of source window */
  23         unsigned        h;              /* Height of source window */
  24         unsigned        stride;         /* Number of bytes per line */
  25         unsigned        out_x;          /* Left edge of output window (col) */
  26         unsigned        out_y;          /* Top edge of output window (row) */
  27         unsigned        out_w;          /* Width of output window in pixels */
  28         unsigned        out_h;          /* Height of output window in pixels */
  29 };
  30
  31 #define FDT_LCD_TIMINGS 4
  32
  33 enum {
  34         FDT_LCD_TIMING_REF_TO_SYNC,
  35         FDT_LCD_TIMING_SYNC_WIDTH,
  36         FDT_LCD_TIMING_BACK_PORCH,
  37         FDT_LCD_TIMING_FRONT_PORCH,
  38
  39         FDT_LCD_TIMING_COUNT,
  40 };
  41
  42 enum lcd_cache_t {
  43         FDT_LCD_CACHE_OFF               = 0,
  44         FDT_LCD_CACHE_WRITE_THROUGH     = 1 << 0,
  45         FDT_LCD_CACHE_WRITE_BACK        = 1 << 1,
  46         FDT_LCD_CACHE_FLUSH             = 1 << 2,
  47         FDT_LCD_CACHE_WRITE_BACK_FLUSH  = FDT_LCD_CACHE_WRITE_BACK |
  48                                                 FDT_LCD_CACHE_FLUSH,
  49 };
  50
  51 #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/