2 * Copyright (c) 2013 Xilinx Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARCH_HARDWARE_H
8 #define _ASM_ARCH_HARDWARE_H
10 #define ZYNQ_SERIAL_BASEADDR0 0xE0000000
11 #define ZYNQ_SERIAL_BASEADDR1 0xE0001000
12 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
13 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
14 #define ZYNQ_SCU_BASEADDR 0xF8F00000
15 #define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600
16 #define ZYNQ_GEM_BASEADDR0 0xE000B000
17 #define ZYNQ_GEM_BASEADDR1 0xE000C000
18 #define ZYNQ_SDHCI_BASEADDR0 0xE0100000
19 #define ZYNQ_SDHCI_BASEADDR1 0xE0101000
20 #define ZYNQ_I2C_BASEADDR0 0xE0004000
21 #define ZYNQ_I2C_BASEADDR1 0xE0005000
22 #define ZYNQ_SPI_BASEADDR0 0xE0006000
23 #define ZYNQ_SPI_BASEADDR1 0xE0007000
24 #define ZYNQ_DDRC_BASEADDR 0xF8006000
25 #define ZYNQ_EFUSE_BASEADDR 0xF800D000
26 #define ZYNQ_USB_BASEADDR0 0xE0002000
27 #define ZYNQ_USB_BASEADDR1 0xE0003000
29 /* Bootmode setting values */
30 #define ZYNQ_BM_MASK 0x7
31 #define ZYNQ_BM_NOR 0x2
32 #define ZYNQ_BM_SD 0x5
33 #define ZYNQ_BM_JTAG 0x0
35 /* Reflect slcr offsets */
38 u32 slcr_lock; /* 0x4 */
39 u32 slcr_unlock; /* 0x8 */
41 u32 arm_pll_ctrl; /* 0x100 */
42 u32 ddr_pll_ctrl; /* 0x104 */
43 u32 io_pll_ctrl; /* 0x108 */
45 u32 arm_clk_ctrl; /* 0x120 */
46 u32 ddr_clk_ctrl; /* 0x124 */
47 u32 dci_clk_ctrl; /* 0x128 */
48 u32 aper_clk_ctrl; /* 0x12c */
50 u32 gem0_rclk_ctrl; /* 0x138 */
51 u32 gem1_rclk_ctrl; /* 0x13c */
52 u32 gem0_clk_ctrl; /* 0x140 */
53 u32 gem1_clk_ctrl; /* 0x144 */
54 u32 smc_clk_ctrl; /* 0x148 */
55 u32 lqspi_clk_ctrl; /* 0x14c */
56 u32 sdio_clk_ctrl; /* 0x150 */
57 u32 uart_clk_ctrl; /* 0x154 */
58 u32 spi_clk_ctrl; /* 0x158 */
59 u32 can_clk_ctrl; /* 0x15c */
60 u32 can_mioclk_ctrl; /* 0x160 */
61 u32 dbg_clk_ctrl; /* 0x164 */
62 u32 pcap_clk_ctrl; /* 0x168 */
64 u32 fpga0_clk_ctrl; /* 0x170 */
66 u32 fpga1_clk_ctrl; /* 0x180 */
68 u32 fpga2_clk_ctrl; /* 0x190 */
70 u32 fpga3_clk_ctrl; /* 0x1a0 */
72 u32 clk_621_true; /* 0x1c4 */
74 u32 pss_rst_ctrl; /* 0x200 */
76 u32 fpga_rst_ctrl; /* 0x240 */
78 u32 reboot_status; /* 0x258 */
79 u32 boot_mode; /* 0x25c */
81 u32 trust_zone; /* 0x430 */ /* FIXME */
83 u32 pss_idcode; /* 0x530 */
85 u32 ddr_urgent; /* 0x600 */
87 u32 ddr_urgent_sel; /* 0x61c */
89 u32 mio_pin[54]; /* 0x700 - 0x7D4 */
91 u32 lvl_shftr_en; /* 0x900 */
93 u32 ocm_cfg; /* 0x910 */
96 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
102 u32 int_sts; /* 0xc */
103 u32 int_mask; /* 0x10 */
104 u32 status; /* 0x14 */
105 u32 dma_src_addr; /* 0x18 */
106 u32 dma_dst_addr; /* 0x1c */
107 u32 dma_src_len; /* 0x20 */
108 u32 dma_dst_len; /* 0x24 */
109 u32 rom_shadow; /* 0x28 */
111 u32 unlock; /* 0x34 */
113 u32 mctrl; /* 0x80 */
115 u32 write_count; /* 0x88 */
116 u32 read_count; /* 0x8c */
119 #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
123 u32 filter_start; /* 0x40 */
124 u32 filter_end; /* 0x44 */
127 #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
130 u32 ddrc_ctrl; /* 0x0 */
132 u32 ecc_scrub; /* 0xF4 */
134 #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
142 #define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
144 #endif /* _ASM_ARCH_HARDWARE_H */