2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
11 #define ZYNQ_SERIAL_BASEADDR0 0xFF000000
12 #define ZYNQ_SERIAL_BASEADDR1 0xFF001000
14 #define ZYNQ_SDHCI_BASEADDR0 0xFF160000
15 #define ZYNQ_SDHCI_BASEADDR1 0xFF170000
17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
22 u32 cpu_r5_ctrl; /* 0x90 */
24 u32 timestamp_ref_ctrl; /* 0x128 */
26 u32 boot_mode; /* 0x200 */
28 u32 rst_lpd_top; /* 0x23C */
32 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
34 #define ZYNQMP_IOU_SCNTR 0xFF250000
35 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
36 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
39 u32 counter_control_register;
41 u32 base_frequency_id_register;
44 #define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
46 /* Bootmode setting values */
47 #define BOOT_MODES_MASK 0x0000000F
48 #define SD_MODE 0x00000003
49 #define EMMC_MODE 0x00000006
50 #define JTAG_MODE 0x00000000
52 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000
57 u32 rpu0_cfg; /* 0x100 */
59 u32 rpu1_cfg; /* 0x200 */
62 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
64 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000
68 u32 rst_fpd_apu; /* 0x104 */
72 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
74 #define ZYNQMP_APU_BASEADDR 0xFD5C0000
78 u32 rvbar_addr0_l; /* 0x40 */
79 u32 rvbar_addr0_h; /* 0x44 */
83 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
85 /* Board version value */
86 #define ZYNQMP_CSU_VERSION_SILICON 0x0
87 #define ZYNQMP_CSU_VERSION_EP108 0x1
88 #define ZYNQMP_CSU_VERSION_VELOCE 0x2
89 #define ZYNQMP_CSU_VERSION_QEMU 0x3
91 #endif /* _ASM_ARCH_HARDWARE_H */