1 #ifndef __ASM_ARM_CMPXCHG_H
2 #define __ASM_ARM_CMPXCHG_H
4 #include <linux/irqflags.h>
5 #include <linux/prefetch.h>
6 #include <asm/barrier.h>
8 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
10 * On the StrongARM, "swp" is terminally broken since it bypasses the
11 * cache totally. This means that the cache becomes inconsistent, and,
12 * since we use normal loads/stores as well, this is really bad.
13 * Typically, this causes oopsen in filp_close, but could have other,
14 * more disastrous effects. There are two work-arounds:
15 * 1. Disable interrupts and emulate the atomic swap
16 * 2. Clean the cache, perform atomic swap, flush the cache
18 * We choose (1) since its the "easiest" to achieve here and is not
19 * dependent on the processor type.
21 * NOTE that this solution won't work on an SMP system, so explcitly
27 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
29 extern void __bad_xchg(volatile void *, int);
34 #if __LINUX_ARM_ARCH__ >= 6
39 prefetchw((const void *)ptr);
42 #if __LINUX_ARM_ARCH__ >= 6
44 asm volatile("@ __xchg1\n"
45 "1: ldrexb %0, [%3]\n"
46 " strexb %1, %2, [%3]\n"
49 : "=&r" (ret), "=&r" (tmp)
54 asm volatile("@ __xchg4\n"
56 " strex %1, %2, [%3]\n"
59 : "=&r" (ret), "=&r" (tmp)
63 #elif defined(swp_is_buggy)
65 #error SMP is not supported on this platform
68 raw_local_irq_save(flags);
69 ret = *(volatile unsigned char *)ptr;
70 *(volatile unsigned char *)ptr = x;
71 raw_local_irq_restore(flags);
75 raw_local_irq_save(flags);
76 ret = *(volatile unsigned long *)ptr;
77 *(volatile unsigned long *)ptr = x;
78 raw_local_irq_restore(flags);
82 asm volatile("@ __xchg1\n"
89 asm volatile("@ __xchg4\n"
97 /* Cause a link-time error, the xchg() size is not supported */
98 __bad_xchg(ptr, size), ret = 0;
106 #define xchg(ptr, x) ({ \
107 (__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), \
111 #include <asm-generic/cmpxchg-local.h>
113 #if __LINUX_ARM_ARCH__ < 6
114 /* min ARCH < ARMv6 */
117 #error "SMP is not supported on this platform"
121 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
124 #define cmpxchg_local(ptr, o, n) ({ \
125 (__typeof(*ptr))__cmpxchg_local_generic((ptr), \
126 (unsigned long)(o), \
127 (unsigned long)(n), \
131 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
133 #include <asm-generic/cmpxchg.h>
135 #else /* min ARCH >= ARMv6 */
137 extern void __bad_cmpxchg(volatile void *ptr, int size);
140 * cmpxchg only support 32-bits operands on ARMv6.
143 static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
144 unsigned long new, int size)
146 unsigned long oldval, res;
148 prefetchw((const void *)ptr);
151 #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
154 asm volatile("@ __cmpxchg1\n"
158 " strexbeq %0, %4, [%2]\n"
159 : "=&r" (res), "=&r" (oldval)
160 : "r" (ptr), "Ir" (old), "r" (new)
166 asm volatile("@ __cmpxchg1\n"
170 " strexheq %0, %4, [%2]\n"
171 : "=&r" (res), "=&r" (oldval)
172 : "r" (ptr), "Ir" (old), "r" (new)
179 asm volatile("@ __cmpxchg4\n"
183 " strexeq %0, %4, [%2]\n"
184 : "=&r" (res), "=&r" (oldval)
185 : "r" (ptr), "Ir" (old), "r" (new)
190 __bad_cmpxchg(ptr, size);
197 static inline unsigned long __cmpxchg_mb(volatile void *ptr, unsigned long old,
198 unsigned long new, int size)
203 ret = __cmpxchg(ptr, old, new, size);
209 #define cmpxchg(ptr,o,n) ({ \
210 (__typeof__(*(ptr)))__cmpxchg_mb((ptr), \
211 (unsigned long)(o), \
212 (unsigned long)(n), \
216 static inline unsigned long __cmpxchg_local(volatile void *ptr,
218 unsigned long new, int size)
223 #ifdef CONFIG_CPU_V6 /* min ARCH == ARMv6 */
226 ret = __cmpxchg_local_generic(ptr, old, new, size);
230 ret = __cmpxchg(ptr, old, new, size);
236 #define cmpxchg_local(ptr, o, n) ({ \
237 (__typeof(*ptr))__cmpxchg_local((ptr), \
238 (unsigned long)(o), \
239 (unsigned long)(n), \
243 static inline unsigned long long __cmpxchg64(unsigned long long *ptr,
244 unsigned long long old,
245 unsigned long long new)
247 unsigned long long oldval;
252 __asm__ __volatile__(
253 "1: ldrexd %1, %H1, [%3]\n"
257 " strexd %0, %5, %H5, [%3]\n"
261 : "=&r" (res), "=&r" (oldval), "+Qo" (*ptr)
262 : "r" (ptr), "r" (old), "r" (new)
268 #define cmpxchg64_relaxed(ptr, o, n) ({ \
269 (__typeof__(*(ptr)))__cmpxchg64((ptr), \
270 (unsigned long long)(o), \
271 (unsigned long long)(n)); \
274 #define cmpxchg64_local(ptr, o, n) cmpxchg64_relaxed((ptr), (o), (n))
276 static inline unsigned long long __cmpxchg64_mb(unsigned long long *ptr,
277 unsigned long long old,
278 unsigned long long new)
280 unsigned long long ret;
283 ret = __cmpxchg64(ptr, old, new);
289 #define cmpxchg64(ptr, o, n) ({ \
290 (__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
291 (unsigned long long)(o), \
292 (unsigned long long)(n)); \
295 #endif /* __LINUX_ARM_ARCH__ >= 6 */
297 #endif /* __ASM_ARM_CMPXCHG_H */