4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
6 * Aneesh V <aneesh@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
15 #include <asm/types.h>
19 #define EMIF1_BASE 0x4c000000
20 #define EMIF2_BASE 0x4d000000
22 /* Registers shifts and masks */
25 #define EMIF_REG_SCHEME_SHIFT 30
26 #define EMIF_REG_SCHEME_MASK (0x3 << 30)
27 #define EMIF_REG_MODULE_ID_SHIFT 16
28 #define EMIF_REG_MODULE_ID_MASK (0xfff << 16)
29 #define EMIF_REG_RTL_VERSION_SHIFT 11
30 #define EMIF_REG_RTL_VERSION_MASK (0x1f << 11)
31 #define EMIF_REG_MAJOR_REVISION_SHIFT 8
32 #define EMIF_REG_MAJOR_REVISION_MASK (0x7 << 8)
33 #define EMIF_REG_MINOR_REVISION_SHIFT 0
34 #define EMIF_REG_MINOR_REVISION_MASK (0x3f << 0)
37 #define EMIF_REG_BE_SHIFT 31
38 #define EMIF_REG_BE_MASK (1 << 31)
39 #define EMIF_REG_DUAL_CLK_MODE_SHIFT 30
40 #define EMIF_REG_DUAL_CLK_MODE_MASK (1 << 30)
41 #define EMIF_REG_FAST_INIT_SHIFT 29
42 #define EMIF_REG_FAST_INIT_MASK (1 << 29)
43 #define EMIF_REG_PHY_DLL_READY_SHIFT 2
44 #define EMIF_REG_PHY_DLL_READY_MASK (1 << 2)
47 #define EMIF_REG_SDRAM_TYPE_SHIFT 29
48 #define EMIF_REG_SDRAM_TYPE_MASK (0x7 << 29)
49 #define EMIF_REG_IBANK_POS_SHIFT 27
50 #define EMIF_REG_IBANK_POS_MASK (0x3 << 27)
51 #define EMIF_REG_DDR_TERM_SHIFT 24
52 #define EMIF_REG_DDR_TERM_MASK (0x7 << 24)
53 #define EMIF_REG_DDR2_DDQS_SHIFT 23
54 #define EMIF_REG_DDR2_DDQS_MASK (1 << 23)
55 #define EMIF_REG_DYN_ODT_SHIFT 21
56 #define EMIF_REG_DYN_ODT_MASK (0x3 << 21)
57 #define EMIF_REG_DDR_DISABLE_DLL_SHIFT 20
58 #define EMIF_REG_DDR_DISABLE_DLL_MASK (1 << 20)
59 #define EMIF_REG_SDRAM_DRIVE_SHIFT 18
60 #define EMIF_REG_SDRAM_DRIVE_MASK (0x3 << 18)
61 #define EMIF_REG_CWL_SHIFT 16
62 #define EMIF_REG_CWL_MASK (0x3 << 16)
63 #define EMIF_REG_NARROW_MODE_SHIFT 14
64 #define EMIF_REG_NARROW_MODE_MASK (0x3 << 14)
65 #define EMIF_REG_CL_SHIFT 10
66 #define EMIF_REG_CL_MASK (0xf << 10)
67 #define EMIF_REG_ROWSIZE_SHIFT 7
68 #define EMIF_REG_ROWSIZE_MASK (0x7 << 7)
69 #define EMIF_REG_IBANK_SHIFT 4
70 #define EMIF_REG_IBANK_MASK (0x7 << 4)
71 #define EMIF_REG_EBANK_SHIFT 3
72 #define EMIF_REG_EBANK_MASK (1 << 3)
73 #define EMIF_REG_PAGESIZE_SHIFT 0
74 #define EMIF_REG_PAGESIZE_MASK (0x7 << 0)
77 #define EMIF_REG_CS1NVMEN_SHIFT 30
78 #define EMIF_REG_CS1NVMEN_MASK (1 << 30)
79 #define EMIF_REG_EBANK_POS_SHIFT 27
80 #define EMIF_REG_EBANK_POS_MASK (1 << 27)
81 #define EMIF_REG_RDBNUM_SHIFT 4
82 #define EMIF_REG_RDBNUM_MASK (0x3 << 4)
83 #define EMIF_REG_RDBSIZE_SHIFT 0
84 #define EMIF_REG_RDBSIZE_MASK (0x7 << 0)
87 #define EMIF_REG_INITREF_DIS_SHIFT 31
88 #define EMIF_REG_INITREF_DIS_MASK (1 << 31)
89 #define EMIF_REG_SRT_SHIFT 29
90 #define EMIF_REG_SRT_MASK (1 << 29)
91 #define EMIF_REG_ASR_SHIFT 28
92 #define EMIF_REG_ASR_MASK (1 << 28)
93 #define EMIF_REG_PASR_SHIFT 24
94 #define EMIF_REG_PASR_MASK (0x7 << 24)
95 #define EMIF_REG_REFRESH_RATE_SHIFT 0
96 #define EMIF_REG_REFRESH_RATE_MASK (0xffff << 0)
98 /* SDRAM_REF_CTRL_SHDW */
99 #define EMIF_REG_REFRESH_RATE_SHDW_SHIFT 0
100 #define EMIF_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0)
103 #define EMIF_REG_T_RP_SHIFT 25
104 #define EMIF_REG_T_RP_MASK (0xf << 25)
105 #define EMIF_REG_T_RCD_SHIFT 21
106 #define EMIF_REG_T_RCD_MASK (0xf << 21)
107 #define EMIF_REG_T_WR_SHIFT 17
108 #define EMIF_REG_T_WR_MASK (0xf << 17)
109 #define EMIF_REG_T_RAS_SHIFT 12
110 #define EMIF_REG_T_RAS_MASK (0x1f << 12)
111 #define EMIF_REG_T_RC_SHIFT 6
112 #define EMIF_REG_T_RC_MASK (0x3f << 6)
113 #define EMIF_REG_T_RRD_SHIFT 3
114 #define EMIF_REG_T_RRD_MASK (0x7 << 3)
115 #define EMIF_REG_T_WTR_SHIFT 0
116 #define EMIF_REG_T_WTR_MASK (0x7 << 0)
118 /* SDRAM_TIM_1_SHDW */
119 #define EMIF_REG_T_RP_SHDW_SHIFT 25
120 #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
121 #define EMIF_REG_T_RCD_SHDW_SHIFT 21
122 #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
123 #define EMIF_REG_T_WR_SHDW_SHIFT 17
124 #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
125 #define EMIF_REG_T_RAS_SHDW_SHIFT 12
126 #define EMIF_REG_T_RAS_SHDW_MASK (0x1f << 12)
127 #define EMIF_REG_T_RC_SHDW_SHIFT 6
128 #define EMIF_REG_T_RC_SHDW_MASK (0x3f << 6)
129 #define EMIF_REG_T_RRD_SHDW_SHIFT 3
130 #define EMIF_REG_T_RRD_SHDW_MASK (0x7 << 3)
131 #define EMIF_REG_T_WTR_SHDW_SHIFT 0
132 #define EMIF_REG_T_WTR_SHDW_MASK (0x7 << 0)
135 #define EMIF_REG_T_XP_SHIFT 28
136 #define EMIF_REG_T_XP_MASK (0x7 << 28)
137 #define EMIF_REG_T_ODT_SHIFT 25
138 #define EMIF_REG_T_ODT_MASK (0x7 << 25)
139 #define EMIF_REG_T_XSNR_SHIFT 16
140 #define EMIF_REG_T_XSNR_MASK (0x1ff << 16)
141 #define EMIF_REG_T_XSRD_SHIFT 6
142 #define EMIF_REG_T_XSRD_MASK (0x3ff << 6)
143 #define EMIF_REG_T_RTP_SHIFT 3
144 #define EMIF_REG_T_RTP_MASK (0x7 << 3)
145 #define EMIF_REG_T_CKE_SHIFT 0
146 #define EMIF_REG_T_CKE_MASK (0x7 << 0)
148 /* SDRAM_TIM_2_SHDW */
149 #define EMIF_REG_T_XP_SHDW_SHIFT 28
150 #define EMIF_REG_T_XP_SHDW_MASK (0x7 << 28)
151 #define EMIF_REG_T_ODT_SHDW_SHIFT 25
152 #define EMIF_REG_T_ODT_SHDW_MASK (0x7 << 25)
153 #define EMIF_REG_T_XSNR_SHDW_SHIFT 16
154 #define EMIF_REG_T_XSNR_SHDW_MASK (0x1ff << 16)
155 #define EMIF_REG_T_XSRD_SHDW_SHIFT 6
156 #define EMIF_REG_T_XSRD_SHDW_MASK (0x3ff << 6)
157 #define EMIF_REG_T_RTP_SHDW_SHIFT 3
158 #define EMIF_REG_T_RTP_SHDW_MASK (0x7 << 3)
159 #define EMIF_REG_T_CKE_SHDW_SHIFT 0
160 #define EMIF_REG_T_CKE_SHDW_MASK (0x7 << 0)
163 #define EMIF_REG_T_CKESR_SHIFT 21
164 #define EMIF_REG_T_CKESR_MASK (0x7 << 21)
165 #define EMIF_REG_ZQ_ZQCS_SHIFT 15
166 #define EMIF_REG_ZQ_ZQCS_MASK (0x3f << 15)
167 #define EMIF_REG_T_TDQSCKMAX_SHIFT 13
168 #define EMIF_REG_T_TDQSCKMAX_MASK (0x3 << 13)
169 #define EMIF_REG_T_RFC_SHIFT 4
170 #define EMIF_REG_T_RFC_MASK (0x1ff << 4)
171 #define EMIF_REG_T_RAS_MAX_SHIFT 0
172 #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
174 /* SDRAM_TIM_3_SHDW */
175 #define EMIF_REG_T_CKESR_SHDW_SHIFT 21
176 #define EMIF_REG_T_CKESR_SHDW_MASK (0x7 << 21)
177 #define EMIF_REG_ZQ_ZQCS_SHDW_SHIFT 15
178 #define EMIF_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15)
179 #define EMIF_REG_T_TDQSCKMAX_SHDW_SHIFT 13
180 #define EMIF_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13)
181 #define EMIF_REG_T_RFC_SHDW_SHIFT 4
182 #define EMIF_REG_T_RFC_SHDW_MASK (0x1ff << 4)
183 #define EMIF_REG_T_RAS_MAX_SHDW_SHIFT 0
184 #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
187 #define EMIF_REG_NVM_T_XP_SHIFT 28
188 #define EMIF_REG_NVM_T_XP_MASK (0x7 << 28)
189 #define EMIF_REG_NVM_T_WTR_SHIFT 24
190 #define EMIF_REG_NVM_T_WTR_MASK (0x7 << 24)
191 #define EMIF_REG_NVM_T_RP_SHIFT 20
192 #define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
193 #define EMIF_REG_NVM_T_WRA_SHIFT 16
194 #define EMIF_REG_NVM_T_WRA_MASK (0xf << 16)
195 #define EMIF_REG_NVM_T_RRD_SHIFT 8
196 #define EMIF_REG_NVM_T_RRD_MASK (0xff << 8)
197 #define EMIF_REG_NVM_T_RCDMIN_SHIFT 0
198 #define EMIF_REG_NVM_T_RCDMIN_MASK (0xff << 0)
200 /* LPDDR2_NVM_TIM_SHDW */
201 #define EMIF_REG_NVM_T_XP_SHDW_SHIFT 28
202 #define EMIF_REG_NVM_T_XP_SHDW_MASK (0x7 << 28)
203 #define EMIF_REG_NVM_T_WTR_SHDW_SHIFT 24
204 #define EMIF_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24)
205 #define EMIF_REG_NVM_T_RP_SHDW_SHIFT 20
206 #define EMIF_REG_NVM_T_RP_SHDW_MASK (0xf << 20)
207 #define EMIF_REG_NVM_T_WRA_SHDW_SHIFT 16
208 #define EMIF_REG_NVM_T_WRA_SHDW_MASK (0xf << 16)
209 #define EMIF_REG_NVM_T_RRD_SHDW_SHIFT 8
210 #define EMIF_REG_NVM_T_RRD_SHDW_MASK (0xff << 8)
211 #define EMIF_REG_NVM_T_RCDMIN_SHDW_SHIFT 0
212 #define EMIF_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0)
215 #define EMIF_REG_IDLEMODE_SHIFT 30
216 #define EMIF_REG_IDLEMODE_MASK (0x3 << 30)
217 #define EMIF_REG_PD_TIM_SHIFT 12
218 #define EMIF_REG_PD_TIM_MASK (0xf << 12)
219 #define EMIF_REG_DPD_EN_SHIFT 11
220 #define EMIF_REG_DPD_EN_MASK (1 << 11)
221 #define EMIF_REG_LP_MODE_SHIFT 8
222 #define EMIF_REG_LP_MODE_MASK (0x7 << 8)
223 #define EMIF_REG_SR_TIM_SHIFT 4
224 #define EMIF_REG_SR_TIM_MASK (0xf << 4)
225 #define EMIF_REG_CS_TIM_SHIFT 0
226 #define EMIF_REG_CS_TIM_MASK (0xf << 0)
228 /* PWR_MGMT_CTRL_SHDW */
229 #define EMIF_REG_PD_TIM_SHDW_SHIFT 12
230 #define EMIF_REG_PD_TIM_SHDW_MASK (0xf << 12)
231 #define EMIF_REG_SR_TIM_SHDW_SHIFT 4
232 #define EMIF_REG_SR_TIM_SHDW_MASK (0xf << 4)
233 #define EMIF_REG_CS_TIM_SHDW_SHIFT 0
234 #define EMIF_REG_CS_TIM_SHDW_MASK (0xf << 0)
236 /* LPDDR2_MODE_REG_DATA */
237 #define EMIF_REG_VALUE_0_SHIFT 0
238 #define EMIF_REG_VALUE_0_MASK (0x7f << 0)
240 /* LPDDR2_MODE_REG_CFG */
241 #define EMIF_REG_CS_SHIFT 31
242 #define EMIF_REG_CS_MASK (1 << 31)
243 #define EMIF_REG_REFRESH_EN_SHIFT 30
244 #define EMIF_REG_REFRESH_EN_MASK (1 << 30)
245 #define EMIF_REG_ADDRESS_SHIFT 0
246 #define EMIF_REG_ADDRESS_MASK (0xff << 0)
249 #define EMIF_REG_SYS_THRESH_MAX_SHIFT 24
250 #define EMIF_REG_SYS_THRESH_MAX_MASK (0xf << 24)
251 #define EMIF_REG_MPU_THRESH_MAX_SHIFT 20
252 #define EMIF_REG_MPU_THRESH_MAX_MASK (0xf << 20)
253 #define EMIF_REG_LL_THRESH_MAX_SHIFT 16
254 #define EMIF_REG_LL_THRESH_MAX_MASK (0xf << 16)
255 #define EMIF_REG_PR_OLD_COUNT_SHIFT 0
256 #define EMIF_REG_PR_OLD_COUNT_MASK (0xff << 0)
259 #define EMIF_REG_SYS_BUS_WIDTH_SHIFT 30
260 #define EMIF_REG_SYS_BUS_WIDTH_MASK (0x3 << 30)
261 #define EMIF_REG_LL_BUS_WIDTH_SHIFT 28
262 #define EMIF_REG_LL_BUS_WIDTH_MASK (0x3 << 28)
263 #define EMIF_REG_WR_FIFO_DEPTH_SHIFT 8
264 #define EMIF_REG_WR_FIFO_DEPTH_MASK (0xff << 8)
265 #define EMIF_REG_CMD_FIFO_DEPTH_SHIFT 0
266 #define EMIF_REG_CMD_FIFO_DEPTH_MASK (0xff << 0)
269 #define EMIF_REG_RREG_FIFO_DEPTH_SHIFT 16
270 #define EMIF_REG_RREG_FIFO_DEPTH_MASK (0xff << 16)
271 #define EMIF_REG_RSD_FIFO_DEPTH_SHIFT 8
272 #define EMIF_REG_RSD_FIFO_DEPTH_MASK (0xff << 8)
273 #define EMIF_REG_RCMD_FIFO_DEPTH_SHIFT 0
274 #define EMIF_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0)
277 #define EMIF_REG_TLEC_SHIFT 16
278 #define EMIF_REG_TLEC_MASK (0xffff << 16)
279 #define EMIF_REG_MT_SHIFT 14
280 #define EMIF_REG_MT_MASK (1 << 14)
281 #define EMIF_REG_ACT_CAP_EN_SHIFT 13
282 #define EMIF_REG_ACT_CAP_EN_MASK (1 << 13)
283 #define EMIF_REG_OPG_LD_SHIFT 12
284 #define EMIF_REG_OPG_LD_MASK (1 << 12)
285 #define EMIF_REG_RESET_PHY_SHIFT 10
286 #define EMIF_REG_RESET_PHY_MASK (1 << 10)
287 #define EMIF_REG_MMS_SHIFT 8
288 #define EMIF_REG_MMS_MASK (1 << 8)
289 #define EMIF_REG_MC_SHIFT 4
290 #define EMIF_REG_MC_MASK (0x3 << 4)
291 #define EMIF_REG_PC_SHIFT 1
292 #define EMIF_REG_PC_MASK (0x7 << 1)
293 #define EMIF_REG_TM_SHIFT 0
294 #define EMIF_REG_TM_MASK (1 << 0)
296 /* IODFT_CTRL_MISR_RSLT */
297 #define EMIF_REG_DQM_TLMR_SHIFT 16
298 #define EMIF_REG_DQM_TLMR_MASK (0x3ff << 16)
299 #define EMIF_REG_CTL_TLMR_SHIFT 0
300 #define EMIF_REG_CTL_TLMR_MASK (0x7ff << 0)
302 /* IODFT_ADDR_MISR_RSLT */
303 #define EMIF_REG_ADDR_TLMR_SHIFT 0
304 #define EMIF_REG_ADDR_TLMR_MASK (0x1fffff << 0)
306 /* IODFT_DATA_MISR_RSLT_1 */
307 #define EMIF_REG_DATA_TLMR_31_0_SHIFT 0
308 #define EMIF_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0)
310 /* IODFT_DATA_MISR_RSLT_2 */
311 #define EMIF_REG_DATA_TLMR_63_32_SHIFT 0
312 #define EMIF_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0)
314 /* IODFT_DATA_MISR_RSLT_3 */
315 #define EMIF_REG_DATA_TLMR_66_64_SHIFT 0
316 #define EMIF_REG_DATA_TLMR_66_64_MASK (0x7 << 0)
319 #define EMIF_REG_COUNTER1_SHIFT 0
320 #define EMIF_REG_COUNTER1_MASK (0xffffffff << 0)
323 #define EMIF_REG_COUNTER2_SHIFT 0
324 #define EMIF_REG_COUNTER2_MASK (0xffffffff << 0)
327 #define EMIF_REG_CNTR2_MCONNID_EN_SHIFT 31
328 #define EMIF_REG_CNTR2_MCONNID_EN_MASK (1 << 31)
329 #define EMIF_REG_CNTR2_REGION_EN_SHIFT 30
330 #define EMIF_REG_CNTR2_REGION_EN_MASK (1 << 30)
331 #define EMIF_REG_CNTR2_CFG_SHIFT 16
332 #define EMIF_REG_CNTR2_CFG_MASK (0xf << 16)
333 #define EMIF_REG_CNTR1_MCONNID_EN_SHIFT 15
334 #define EMIF_REG_CNTR1_MCONNID_EN_MASK (1 << 15)
335 #define EMIF_REG_CNTR1_REGION_EN_SHIFT 14
336 #define EMIF_REG_CNTR1_REGION_EN_MASK (1 << 14)
337 #define EMIF_REG_CNTR1_CFG_SHIFT 0
338 #define EMIF_REG_CNTR1_CFG_MASK (0xf << 0)
341 #define EMIF_REG_MCONNID2_SHIFT 24
342 #define EMIF_REG_MCONNID2_MASK (0xff << 24)
343 #define EMIF_REG_REGION_SEL2_SHIFT 16
344 #define EMIF_REG_REGION_SEL2_MASK (0x3 << 16)
345 #define EMIF_REG_MCONNID1_SHIFT 8
346 #define EMIF_REG_MCONNID1_MASK (0xff << 8)
347 #define EMIF_REG_REGION_SEL1_SHIFT 0
348 #define EMIF_REG_REGION_SEL1_MASK (0x3 << 0)
351 #define EMIF_REG_TOTAL_TIME_SHIFT 0
352 #define EMIF_REG_TOTAL_TIME_MASK (0xffffffff << 0)
355 #define EMIF_REG_READ_IDLE_LEN_SHIFT 16
356 #define EMIF_REG_READ_IDLE_LEN_MASK (0xf << 16)
357 #define EMIF_REG_READ_IDLE_INTERVAL_SHIFT 0
358 #define EMIF_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0)
360 /* READ_IDLE_CTRL_SHDW */
361 #define EMIF_REG_READ_IDLE_LEN_SHDW_SHIFT 16
362 #define EMIF_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16)
363 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0
364 #define EMIF_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0)
367 #define EMIF_REG_EOI_SHIFT 0
368 #define EMIF_REG_EOI_MASK (1 << 0)
370 /* IRQSTATUS_RAW_SYS */
371 #define EMIF_REG_DNV_SYS_SHIFT 2
372 #define EMIF_REG_DNV_SYS_MASK (1 << 2)
373 #define EMIF_REG_TA_SYS_SHIFT 1
374 #define EMIF_REG_TA_SYS_MASK (1 << 1)
375 #define EMIF_REG_ERR_SYS_SHIFT 0
376 #define EMIF_REG_ERR_SYS_MASK (1 << 0)
378 /* IRQSTATUS_RAW_LL */
379 #define EMIF_REG_DNV_LL_SHIFT 2
380 #define EMIF_REG_DNV_LL_MASK (1 << 2)
381 #define EMIF_REG_TA_LL_SHIFT 1
382 #define EMIF_REG_TA_LL_MASK (1 << 1)
383 #define EMIF_REG_ERR_LL_SHIFT 0
384 #define EMIF_REG_ERR_LL_MASK (1 << 0)
390 /* IRQENABLE_SET_SYS */
391 #define EMIF_REG_EN_DNV_SYS_SHIFT 2
392 #define EMIF_REG_EN_DNV_SYS_MASK (1 << 2)
393 #define EMIF_REG_EN_TA_SYS_SHIFT 1
394 #define EMIF_REG_EN_TA_SYS_MASK (1 << 1)
395 #define EMIF_REG_EN_ERR_SYS_SHIFT 0
396 #define EMIF_REG_EN_ERR_SYS_MASK (1 << 0)
398 /* IRQENABLE_SET_LL */
399 #define EMIF_REG_EN_DNV_LL_SHIFT 2
400 #define EMIF_REG_EN_DNV_LL_MASK (1 << 2)
401 #define EMIF_REG_EN_TA_LL_SHIFT 1
402 #define EMIF_REG_EN_TA_LL_MASK (1 << 1)
403 #define EMIF_REG_EN_ERR_LL_SHIFT 0
404 #define EMIF_REG_EN_ERR_LL_MASK (1 << 0)
406 /* IRQENABLE_CLR_SYS */
408 /* IRQENABLE_CLR_LL */
411 #define EMIF_REG_ZQ_CS1EN_SHIFT 31
412 #define EMIF_REG_ZQ_CS1EN_MASK (1 << 31)
413 #define EMIF_REG_ZQ_CS0EN_SHIFT 30
414 #define EMIF_REG_ZQ_CS0EN_MASK (1 << 30)
415 #define EMIF_REG_ZQ_DUALCALEN_SHIFT 29
416 #define EMIF_REG_ZQ_DUALCALEN_MASK (1 << 29)
417 #define EMIF_REG_ZQ_SFEXITEN_SHIFT 28
418 #define EMIF_REG_ZQ_SFEXITEN_MASK (1 << 28)
419 #define EMIF_REG_ZQ_ZQINIT_MULT_SHIFT 18
420 #define EMIF_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18)
421 #define EMIF_REG_ZQ_ZQCL_MULT_SHIFT 16
422 #define EMIF_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16)
423 #define EMIF_REG_ZQ_REFINTERVAL_SHIFT 0
424 #define EMIF_REG_ZQ_REFINTERVAL_MASK (0xffff << 0)
426 /* TEMP_ALERT_CONFIG */
427 #define EMIF_REG_TA_CS1EN_SHIFT 31
428 #define EMIF_REG_TA_CS1EN_MASK (1 << 31)
429 #define EMIF_REG_TA_CS0EN_SHIFT 30
430 #define EMIF_REG_TA_CS0EN_MASK (1 << 30)
431 #define EMIF_REG_TA_SFEXITEN_SHIFT 28
432 #define EMIF_REG_TA_SFEXITEN_MASK (1 << 28)
433 #define EMIF_REG_TA_DEVWDT_SHIFT 26
434 #define EMIF_REG_TA_DEVWDT_MASK (0x3 << 26)
435 #define EMIF_REG_TA_DEVCNT_SHIFT 24
436 #define EMIF_REG_TA_DEVCNT_MASK (0x3 << 24)
437 #define EMIF_REG_TA_REFINTERVAL_SHIFT 0
438 #define EMIF_REG_TA_REFINTERVAL_MASK (0x3fffff << 0)
441 #define EMIF_REG_MADDRSPACE_SHIFT 14
442 #define EMIF_REG_MADDRSPACE_MASK (0x3 << 14)
443 #define EMIF_REG_MBURSTSEQ_SHIFT 11
444 #define EMIF_REG_MBURSTSEQ_MASK (0x7 << 11)
445 #define EMIF_REG_MCMD_SHIFT 8
446 #define EMIF_REG_MCMD_MASK (0x7 << 8)
447 #define EMIF_REG_MCONNID_SHIFT 0
448 #define EMIF_REG_MCONNID_MASK (0xff << 0)
451 #define EMIF_REG_DDR_PHY_CTRL_1_SHIFT 4
452 #define EMIF_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4)
453 #define EMIF_REG_READ_LATENCY_SHIFT 0
454 #define EMIF_REG_READ_LATENCY_MASK (0xf << 0)
455 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4
456 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4)
457 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12
458 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12)
460 /* DDR_PHY_CTRL_1_SHDW */
461 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4
462 #define EMIF_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4)
463 #define EMIF_REG_READ_LATENCY_SHDW_SHIFT 0
464 #define EMIF_REG_READ_LATENCY_SHDW_MASK (0xf << 0)
465 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4
466 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4)
467 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
468 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12)
471 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0
472 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
474 /*EMIF_READ_WRITE_LEVELING_CONTROL*/
475 #define EMIF_REG_RDWRLVLFULL_START_SHIFT 31
476 #define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31)
477 #define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24
478 #define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24)
479 #define EMIF_REG_RDLVLINC_INT_SHIFT 16
480 #define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16)
481 #define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8
482 #define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8)
483 #define EMIF_REG_WRLVLINC_INT_SHIFT 0
484 #define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0)
486 /*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/
487 #define EMIF_REG_RDWRLVL_EN_SHIFT 31
488 #define EMIF_REG_RDWRLVL_EN_MASK (1 << 31)
489 #define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24
490 #define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24)
491 #define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16
492 #define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16)
493 #define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8
494 #define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8)
495 #define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0
496 #define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0)
498 /*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/
499 #define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0
500 #define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0)
503 #define DDR3_WR_LVL_INT 0x73
504 #define DDR3_RD_LVL_INT 0x33
505 #define DDR3_RD_LVL_GATE_INT 0x59
506 #define RD_RW_LVL_INC_PRE 0x0
507 #define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT)
509 #define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \
510 | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \
511 | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \
512 | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT))
514 #define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7
515 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7
518 #define DMM_BASE 0x4E000040
521 #define MA_BASE 0x482AF040
524 #define EMIF_SYS_ADDR_SHIFT 24
525 #define EMIF_SYS_ADDR_MASK (0xff << 24)
526 #define EMIF_SYS_SIZE_SHIFT 20
527 #define EMIF_SYS_SIZE_MASK (0x7 << 20)
528 #define EMIF_SDRC_INTL_SHIFT 18
529 #define EMIF_SDRC_INTL_MASK (0x3 << 18)
530 #define EMIF_SDRC_ADDRSPC_SHIFT 16
531 #define EMIF_SDRC_ADDRSPC_MASK (0x3 << 16)
532 #define EMIF_SDRC_MAP_SHIFT 8
533 #define EMIF_SDRC_MAP_MASK (0x3 << 8)
534 #define EMIF_SDRC_ADDR_SHIFT 0
535 #define EMIF_SDRC_ADDR_MASK (0xff << 0)
537 /* DMM_LISA_MAP fields */
538 #define DMM_SDRC_MAP_UNMAPPED 0
539 #define DMM_SDRC_MAP_EMIF1_ONLY 1
540 #define DMM_SDRC_MAP_EMIF2_ONLY 2
541 #define DMM_SDRC_MAP_EMIF1_AND_EMIF2 3
543 #define DMM_SDRC_INTL_NONE 0
544 #define DMM_SDRC_INTL_128B 1
545 #define DMM_SDRC_INTL_256B 2
546 #define DMM_SDRC_INTL_512 3
548 #define DMM_SDRC_ADDR_SPC_SDRAM 0
549 #define DMM_SDRC_ADDR_SPC_NVM 1
550 #define DMM_SDRC_ADDR_SPC_INVALID 2
552 #define DMM_LISA_MAP_INTERLEAVED_BASE_VAL (\
553 (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\
554 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\
555 (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\
556 (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT))
558 #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\
559 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
560 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
561 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
563 #define DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL (\
564 (DMM_SDRC_MAP_EMIF2_ONLY << EMIF_SDRC_MAP_SHIFT)|\
565 (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT)|\
566 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT))
568 /* Trap for invalid TILER PAT entries */
569 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP (\
570 (0 << EMIF_SDRC_ADDR_SHIFT) |\
571 (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\
572 (DMM_SDRC_ADDR_SPC_INVALID << EMIF_SDRC_ADDRSPC_SHIFT)|\
573 (DMM_SDRC_INTL_NONE << EMIF_SDRC_INTL_SHIFT)|\
574 (0xFF << EMIF_SYS_ADDR_SHIFT))
576 #define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
577 #define EMIF_EXT_PHY_CTRL_CONST_REG 0x13
579 /* Reg mapping structure */
580 struct emif_reg_struct {
583 u32 emif_sdram_config;
584 u32 emif_lpddr2_nvm_config;
585 u32 emif_sdram_ref_ctrl;
586 u32 emif_sdram_ref_ctrl_shdw;
587 u32 emif_sdram_tim_1;
588 u32 emif_sdram_tim_1_shdw;
589 u32 emif_sdram_tim_2;
590 u32 emif_sdram_tim_2_shdw;
591 u32 emif_sdram_tim_3;
592 u32 emif_sdram_tim_3_shdw;
593 u32 emif_lpddr2_nvm_tim;
594 u32 emif_lpddr2_nvm_tim_shdw;
595 u32 emif_pwr_mgmt_ctrl;
596 u32 emif_pwr_mgmt_ctrl_shdw;
597 u32 emif_lpddr2_mode_reg_data;
599 u32 emif_lpddr2_mode_reg_data_es2;
601 u32 emif_lpddr2_mode_reg_cfg;
603 u32 emif_l3_cfg_val_1;
604 u32 emif_l3_cfg_val_2;
609 u32 emif_perf_cnt_cfg;
610 u32 emif_perf_cnt_sel;
611 u32 emif_perf_cnt_tim;
613 u32 emif_read_idlectrl;
614 u32 emif_read_idlectrl_shdw;
616 u32 emif_irqstatus_raw_sys;
617 u32 emif_irqstatus_raw_ll;
618 u32 emif_irqstatus_sys;
619 u32 emif_irqstatus_ll;
620 u32 emif_irqenable_set_sys;
621 u32 emif_irqenable_set_ll;
622 u32 emif_irqenable_clr_sys;
623 u32 emif_irqenable_clr_ll;
626 u32 emif_temp_alert_config;
628 u32 emif_rd_wr_lvl_rmp_win;
629 u32 emif_rd_wr_lvl_rmp_ctl;
630 u32 emif_rd_wr_lvl_ctl;
632 u32 emif_ddr_phy_ctrl_1;
633 u32 emif_ddr_phy_ctrl_1_shdw;
634 u32 emif_ddr_phy_ctrl_2;
636 u32 emif_rd_wr_exec_thresh;
638 u32 emif_ddr_ext_phy_ctrl_1;
639 u32 emif_ddr_ext_phy_ctrl_1_shdw;
640 u32 emif_ddr_ext_phy_ctrl_2;
641 u32 emif_ddr_ext_phy_ctrl_2_shdw;
642 u32 emif_ddr_ext_phy_ctrl_3;
643 u32 emif_ddr_ext_phy_ctrl_3_shdw;
644 u32 emif_ddr_ext_phy_ctrl_4;
645 u32 emif_ddr_ext_phy_ctrl_4_shdw;
646 u32 emif_ddr_ext_phy_ctrl_5;
647 u32 emif_ddr_ext_phy_ctrl_5_shdw;
648 u32 emif_ddr_ext_phy_ctrl_6;
649 u32 emif_ddr_ext_phy_ctrl_6_shdw;
650 u32 emif_ddr_ext_phy_ctrl_7;
651 u32 emif_ddr_ext_phy_ctrl_7_shdw;
652 u32 emif_ddr_ext_phy_ctrl_8;
653 u32 emif_ddr_ext_phy_ctrl_8_shdw;
654 u32 emif_ddr_ext_phy_ctrl_9;
655 u32 emif_ddr_ext_phy_ctrl_9_shdw;
656 u32 emif_ddr_ext_phy_ctrl_10;
657 u32 emif_ddr_ext_phy_ctrl_10_shdw;
658 u32 emif_ddr_ext_phy_ctrl_11;
659 u32 emif_ddr_ext_phy_ctrl_11_shdw;
660 u32 emif_ddr_ext_phy_ctrl_12;
661 u32 emif_ddr_ext_phy_ctrl_12_shdw;
662 u32 emif_ddr_ext_phy_ctrl_13;
663 u32 emif_ddr_ext_phy_ctrl_13_shdw;
664 u32 emif_ddr_ext_phy_ctrl_14;
665 u32 emif_ddr_ext_phy_ctrl_14_shdw;
666 u32 emif_ddr_ext_phy_ctrl_15;
667 u32 emif_ddr_ext_phy_ctrl_15_shdw;
668 u32 emif_ddr_ext_phy_ctrl_16;
669 u32 emif_ddr_ext_phy_ctrl_16_shdw;
670 u32 emif_ddr_ext_phy_ctrl_17;
671 u32 emif_ddr_ext_phy_ctrl_17_shdw;
672 u32 emif_ddr_ext_phy_ctrl_18;
673 u32 emif_ddr_ext_phy_ctrl_18_shdw;
674 u32 emif_ddr_ext_phy_ctrl_19;
675 u32 emif_ddr_ext_phy_ctrl_19_shdw;
676 u32 emif_ddr_ext_phy_ctrl_20;
677 u32 emif_ddr_ext_phy_ctrl_20_shdw;
678 u32 emif_ddr_ext_phy_ctrl_21;
679 u32 emif_ddr_ext_phy_ctrl_21_shdw;
680 u32 emif_ddr_ext_phy_ctrl_22;
681 u32 emif_ddr_ext_phy_ctrl_22_shdw;
682 u32 emif_ddr_ext_phy_ctrl_23;
683 u32 emif_ddr_ext_phy_ctrl_23_shdw;
684 u32 emif_ddr_ext_phy_ctrl_24;
685 u32 emif_ddr_ext_phy_ctrl_24_shdw;
688 struct dmm_lisa_map_regs {
695 extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
696 extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
700 /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
701 #define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */
704 * The period of DDR clk is represented as numerator and denominator for
705 * better accuracy in integer based calculations. However, if the numerator
706 * and denominator are very huge there may be chances of overflow in
707 * calculations. So, as a trade-off keep denominator(and consequently
708 * numerator) within a limit sacrificing some accuracy - but not much
709 * If denominator and numerator are already small (such as at 400 MHz)
710 * no adjustment is needed
712 #define EMIF_PERIOD_DEN_LIMIT 1000
714 * Maximum number of different frequencies supported by EMIF driver
715 * Determines the number of entries in the pointer array for register
718 #define EMIF_MAX_NUM_FREQUENCIES 6
720 * Indices into the Addressing Table array.
721 * One entry each for all the different types of devices with different
724 #define ADDR_TABLE_INDEX64M 0
725 #define ADDR_TABLE_INDEX128M 1
726 #define ADDR_TABLE_INDEX256M 2
727 #define ADDR_TABLE_INDEX512M 3
728 #define ADDR_TABLE_INDEX1GS4 4
729 #define ADDR_TABLE_INDEX2GS4 5
730 #define ADDR_TABLE_INDEX4G 6
731 #define ADDR_TABLE_INDEX8G 7
732 #define ADDR_TABLE_INDEX1GS2 8
733 #define ADDR_TABLE_INDEX2GS2 9
734 #define ADDR_TABLE_INDEXMAX 10
736 /* Number of Row bits */
746 /* Number of Column bits */
751 #define COL_7 4 /*Not supported by OMAP included for completeness */
759 /* Refresh rate in micro seconds x 10 */
760 #define T_REFI_15_6 156
761 #define T_REFI_7_8 78
762 #define T_REFI_3_9 39
764 #define EBANK_CS1_DIS 0
765 #define EBANK_CS1_EN 1
767 /* Read Latency used by the device at reset */
769 /* Read Latency for the highest frequency you want to use */
770 #ifdef CONFIG_OMAP54XX
777 /* Interleaving policies at EMIF level- between banks and Chip Selects */
778 #define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0
779 #define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3
782 * Interleaving policy to be used
783 * Currently set to MAX interleaving for better performance
785 #define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING
787 /* State of the core voltage:
788 * This is important for some parameters such as read idle control and
789 * ZQ calibration timings. Timings are much stricter when voltage ramp
790 * is happening compared to when the voltage is stable.
791 * We need to calculate two sets of values for these parameters and use
794 #define LPDDR2_VOLTAGE_STABLE 0
795 #define LPDDR2_VOLTAGE_RAMPING 1
797 /* Length of the forced read idle period in terms of cycles */
798 #define EMIF_REG_READ_IDLE_LEN_VAL 5
800 /* Interval between forced 'read idles' */
801 /* To be used when voltage is changed for DPS/DVFS - 1us */
802 #define READ_IDLE_INTERVAL_DVFS (1*1000)
804 * To be used when voltage is not scaled except by Smart Reflex
805 * 50us - or maximum value will do
807 #define READ_IDLE_INTERVAL_NORMAL (50*1000)
811 * Unless voltage is changing due to DVFS one ZQCS command every 50ms should
812 * be enough. This shoule be enough also in the case when voltage is changing
813 * due to smart-reflex.
815 #define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000)
817 * If voltage is changing due to DVFS ZQCS should be performed more
820 #define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50
822 /* The interval between ZQCL commands as a multiple of ZQCS interval */
823 #define REG_ZQ_ZQCL_MULT 4
824 /* The interval between ZQINIT commands as a multiple of ZQCL interval */
825 #define REG_ZQ_ZQINIT_MULT 3
826 /* Enable ZQ Calibration on exiting Self-refresh */
827 #define REG_ZQ_SFEXITEN_ENABLE 1
829 * ZQ Calibration simultaneously on both chip-selects:
830 * Needs one calibration resistor per CS
831 * None of the boards that we know of have this capability
832 * So disabled by default
834 #define REG_ZQ_DUALCALEN_DISABLE 0
836 * Enable ZQ Calibration by default on CS0. If we are asked to program
837 * the EMIF there will be something connected to CS0 for sure
839 #define REG_ZQ_CS0EN_ENABLE 1
841 /* EMIF_PWR_MGMT_CTRL register */
842 /* Low power modes */
843 #define LP_MODE_DISABLE 0
844 #define LP_MODE_CLOCK_STOP 1
845 #define LP_MODE_SELF_REFRESH 2
846 #define LP_MODE_PWR_DN 3
849 #define DPD_DISABLE 0
852 /* Maximum delay before Low Power Modes */
853 #ifndef CONFIG_OMAP54XX
854 #define REG_CS_TIM 0xF
856 #define REG_CS_TIM 0x0
858 #define REG_SR_TIM 0xF
859 #define REG_PD_TIM 0xF
861 /* EMIF_PWR_MGMT_CTRL register */
862 #define EMIF_PWR_MGMT_CTRL (\
863 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHIFT) & EMIF_REG_CS_TIM_MASK)|\
864 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHIFT) & EMIF_REG_SR_TIM_MASK)|\
865 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
866 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHIFT) & EMIF_REG_PD_TIM_MASK)|\
867 ((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)\
868 & EMIF_REG_LP_MODE_MASK) |\
869 ((DPD_DISABLE << EMIF_REG_DPD_EN_SHIFT)\
870 & EMIF_REG_DPD_EN_MASK))\
872 #define EMIF_PWR_MGMT_CTRL_SHDW (\
873 ((REG_CS_TIM << EMIF_REG_CS_TIM_SHDW_SHIFT)\
874 & EMIF_REG_CS_TIM_SHDW_MASK) |\
875 ((REG_SR_TIM << EMIF_REG_SR_TIM_SHDW_SHIFT)\
876 & EMIF_REG_SR_TIM_SHDW_MASK) |\
877 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
878 & EMIF_REG_PD_TIM_SHDW_MASK) |\
879 ((REG_PD_TIM << EMIF_REG_PD_TIM_SHDW_SHIFT)\
880 & EMIF_REG_PD_TIM_SHDW_MASK))
882 /* EMIF_L3_CONFIG register value */
883 #define EMIF_L3_CONFIG_VAL_SYS_10_LL_0 0x0A0000FF
884 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0 0x0A300000
885 #define EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0 0x0A500000
888 * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
889 * All these fields have magic values dependent on frequency and
890 * determined by PHY and DLL integration with EMIF. Setting the magic
891 * values suggested by hw team.
893 #define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF
894 #define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41
895 #define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80
896 #define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF
901 * Burst type : sequential
903 * nWR : 3(default). EMIF does not do pre-charge.
904 * : So nWR is don't care
906 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3 0x23
907 #define MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8 0xc3
910 #define MR2_RL3_WL1 1
911 #define MR2_RL4_WL2 2
912 #define MR2_RL5_WL2 3
913 #define MR2_RL6_WL3 4
915 /* MR10: ZQ calibration codes */
916 #define MR10_ZQ_ZQCS 0x56
917 #define MR10_ZQ_ZQCL 0xAB
918 #define MR10_ZQ_ZQINIT 0xFF
919 #define MR10_ZQ_ZQRESET 0xC3
921 /* TEMP_ALERT_CONFIG */
922 #define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */
923 #define TEMP_ALERT_CONFIG_DEVCT_1 0
924 #define TEMP_ALERT_CONFIG_DEVWDT_32 2
926 /* MR16 value: refresh full array(no partial array self refresh) */
927 #define MR16_REF_FULL_ARRAY 0
930 * Maximum number of entries we keep in our array of timing tables
931 * We need not keep all the speed bins supported by the device
932 * We need to keep timing tables for only the speed bins that we
935 #define MAX_NUM_SPEEDBINS 4
937 /* LPDDR2 Densities */
938 #define LPDDR2_DENSITY_64Mb 0
939 #define LPDDR2_DENSITY_128Mb 1
940 #define LPDDR2_DENSITY_256Mb 2
941 #define LPDDR2_DENSITY_512Mb 3
942 #define LPDDR2_DENSITY_1Gb 4
943 #define LPDDR2_DENSITY_2Gb 5
944 #define LPDDR2_DENSITY_4Gb 6
945 #define LPDDR2_DENSITY_8Gb 7
946 #define LPDDR2_DENSITY_16Gb 8
947 #define LPDDR2_DENSITY_32Gb 9
950 #define LPDDR2_TYPE_S4 0
951 #define LPDDR2_TYPE_S2 1
952 #define LPDDR2_TYPE_NVM 2
954 /* LPDDR2 IO width */
955 #define LPDDR2_IO_WIDTH_32 0
956 #define LPDDR2_IO_WIDTH_16 1
957 #define LPDDR2_IO_WIDTH_8 2
959 /* Mode register numbers */
970 #define LPDDR2_MR10 10
971 #define LPDDR2_MR11 11
972 #define LPDDR2_MR16 16
973 #define LPDDR2_MR17 17
974 #define LPDDR2_MR18 18
977 #define LPDDR2_MR0_DAI_SHIFT 0
978 #define LPDDR2_MR0_DAI_MASK 1
979 #define LPDDR2_MR0_DI_SHIFT 1
980 #define LPDDR2_MR0_DI_MASK (1 << 1)
981 #define LPDDR2_MR0_DNVI_SHIFT 2
982 #define LPDDR2_MR0_DNVI_MASK (1 << 2)
985 #define MR4_SDRAM_REF_RATE_SHIFT 0
986 #define MR4_SDRAM_REF_RATE_MASK 7
987 #define MR4_TUF_SHIFT 7
988 #define MR4_TUF_MASK (1 << 7)
990 /* MR4 SDRAM Refresh Rate field values */
991 #define SDRAM_TEMP_LESS_LOW_SHUTDOWN 0x0
992 #define SDRAM_TEMP_LESS_4X_REFRESH_AND_TIMINGS 0x1
993 #define SDRAM_TEMP_LESS_2X_REFRESH_AND_TIMINGS 0x2
994 #define SDRAM_TEMP_NOMINAL 0x3
995 #define SDRAM_TEMP_RESERVED_4 0x4
996 #define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
997 #define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
998 #define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
1000 #define LPDDR2_MANUFACTURER_SAMSUNG 1
1001 #define LPDDR2_MANUFACTURER_QIMONDA 2
1002 #define LPDDR2_MANUFACTURER_ELPIDA 3
1003 #define LPDDR2_MANUFACTURER_ETRON 4
1004 #define LPDDR2_MANUFACTURER_NANYA 5
1005 #define LPDDR2_MANUFACTURER_HYNIX 6
1006 #define LPDDR2_MANUFACTURER_MOSEL 7
1007 #define LPDDR2_MANUFACTURER_WINBOND 8
1008 #define LPDDR2_MANUFACTURER_ESMT 9
1009 #define LPDDR2_MANUFACTURER_SPANSION 11
1010 #define LPDDR2_MANUFACTURER_SST 12
1011 #define LPDDR2_MANUFACTURER_ZMOS 13
1012 #define LPDDR2_MANUFACTURER_INTEL 14
1013 #define LPDDR2_MANUFACTURER_NUMONYX 254
1014 #define LPDDR2_MANUFACTURER_MICRON 255
1016 /* MR8 register fields */
1017 #define MR8_TYPE_SHIFT 0x0
1018 #define MR8_TYPE_MASK 0x3
1019 #define MR8_DENSITY_SHIFT 0x2
1020 #define MR8_DENSITY_MASK (0xF << 0x2)
1021 #define MR8_IO_WIDTH_SHIFT 0x6
1022 #define MR8_IO_WIDTH_MASK (0x3 << 0x6)
1024 struct lpddr2_addressing {
1027 u8 row_sz[2]; /* One entry each for x32 and x16 */
1028 u8 col_sz[2]; /* One entry each for x32 and x16 */
1031 /* Structure for timings from the DDR datasheet */
1032 struct lpddr2_ac_timings {
1057 * Min tCK values for some of the parameters:
1058 * If the calculated clock cycles for the respective parameter is
1059 * less than the corresponding min tCK value, we need to set the min
1060 * tCK value. This may happen at lower frequencies.
1062 struct lpddr2_min_tck {
1077 struct lpddr2_device_details {
1084 struct lpddr2_device_timings {
1085 const struct lpddr2_ac_timings **ac_timings;
1086 const struct lpddr2_min_tck *min_tck;
1089 /* Details of the devices connected to each chip-select of an EMIF instance */
1090 struct emif_device_details {
1091 const struct lpddr2_device_details *cs0_device_details;
1092 const struct lpddr2_device_details *cs1_device_details;
1093 const struct lpddr2_device_timings *cs0_device_timings;
1094 const struct lpddr2_device_timings *cs1_device_timings;
1098 * Structure containing shadow of important registers in EMIF
1099 * The calculation function fills in this structure to be later used for
1100 * initialization and DVFS
1104 u32 sdram_config_init;
1112 u32 temp_alert_config;
1113 u32 emif_ddr_phy_ctlr_1_init;
1114 u32 emif_ddr_phy_ctlr_1;
1115 u32 emif_ddr_ext_phy_ctrl_1;
1116 u32 emif_ddr_ext_phy_ctrl_2;
1117 u32 emif_ddr_ext_phy_ctrl_3;
1118 u32 emif_ddr_ext_phy_ctrl_4;
1119 u32 emif_ddr_ext_phy_ctrl_5;
1120 u32 emif_rd_wr_lvl_rmp_win;
1121 u32 emif_rd_wr_lvl_rmp_ctl;
1122 u32 emif_rd_wr_lvl_ctl;
1123 u32 emif_rd_wr_exec_thresh;
1128 #define emif_assert(c) ({ if (!(c)) for (;;); })
1130 #define emif_assert(c) ({ if (0) hang(); })
1133 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1134 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs);
1135 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs);
1137 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1138 struct lpddr2_device_details *lpddr2_dev_details);
1139 void emif_get_device_timings(u32 emif_nr,
1140 const struct lpddr2_device_timings **cs0_device_timings,
1141 const struct lpddr2_device_timings **cs1_device_timings);
1144 void do_ext_phy_settings(u32 base, const struct emif_regs *regs);
1146 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1147 extern u32 *const T_num;
1148 extern u32 *const T_den;
1149 extern u32 *const emif_sizes;
1152 void config_data_eye_leveling_samples(u32 emif_base);