2 * linux/arch/arm/kernel/bios32.c
4 * PCI bios-type initialisation for PCI machines
6 * Bits taken from various places.
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/slab.h>
12 #include <linux/init.h>
15 #include <asm/mach-types.h>
16 #include <asm/mach/pci.h>
21 * We can't use pci_find_device() here since we are
22 * called from interrupt context.
24 static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
28 list_for_each_entry(dev, &bus->devices, bus_list) {
32 * ignore host bridge - we handle
35 if (dev->bus->number == 0 && dev->devfn == 0)
38 pci_read_config_word(dev, PCI_STATUS, &status);
42 if ((status & status_mask) == 0)
45 /* clear the status errors */
46 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49 printk("(%s: %04X) ", pci_name(dev), status);
52 list_for_each_entry(dev, &bus->devices, bus_list)
54 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
57 void pcibios_report_status(u_int status_mask, int warn)
61 list_for_each(l, &pci_root_buses) {
62 struct pci_bus *bus = pci_bus_b(l);
64 pcibios_bus_report_status(bus, status_mask, warn);
69 * We don't use this to fix the device, but initialisation of it.
70 * It's not the correct use for this, but it works.
71 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
74 * 2. ISA bridge ping-pong
75 * 3. ISA bridge master handling of target RETRY
77 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
80 static void __devinit pci_fixup_83c553(struct pci_dev *dev)
83 * Set memory region to start at address 0, and enable IO
85 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
86 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
88 dev->resource[0].end -= dev->resource[0].start;
89 dev->resource[0].start = 0;
92 * All memory requests from ISA to be channelled to PCI
94 pci_write_config_byte(dev, 0x48, 0xff);
97 * Enable ping-pong on bus master to ISA bridge transactions.
98 * This improves the sound DMA substantially. The fixed
99 * priority arbiter also helps (see below).
101 pci_write_config_byte(dev, 0x42, 0x01);
106 pci_write_config_byte(dev, 0x40, 0x22);
109 * We used to set the arbiter to "park on last master" (bit
110 * 1 set), but unfortunately the CyberPro does not park the
111 * bus. We must therefore park on CPU. Unfortunately, this
112 * may trigger yet another bug in the 553.
114 pci_write_config_byte(dev, 0x83, 0x02);
117 * Make the ISA DMA request lowest priority, and disable
118 * rotating priorities completely.
120 pci_write_config_byte(dev, 0x80, 0x11);
121 pci_write_config_byte(dev, 0x81, 0x00);
124 * Route INTA input to IRQ 11, and set IRQ11 to be level
127 pci_write_config_word(dev, 0x44, 0xb000);
130 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
132 static void __devinit pci_fixup_unassign(struct pci_dev *dev)
134 dev->resource[0].end -= dev->resource[0].start;
135 dev->resource[0].start = 0;
137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
140 * Prevent the PCI layer from seeing the resources allocated to this device
141 * if it is the host bridge by marking it as such. These resources are of
142 * no consequence to the PCI layer (they are handled elsewhere).
144 static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
148 if (dev->devfn == 0) {
150 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
151 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
152 dev->resource[i].start = 0;
153 dev->resource[i].end = 0;
154 dev->resource[i].flags = 0;
158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
161 * PCI IDE controllers use non-standard I/O port decoding, respect it.
163 static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
168 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
171 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
172 r = dev->resource + i;
173 if ((r->start & ~0x80) == 0x374) {
179 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
182 * Put the DEC21142 to sleep
184 static void __devinit pci_fixup_dec21142(struct pci_dev *dev)
186 pci_write_config_dword(dev, 0x40, 0x80000000);
188 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
191 * The CY82C693 needs some rather major fixups to ensure that it does
192 * the right thing. Idea from the Alpha people, with a few additions.
194 * We ensure that the IDE base registers are set to 1f0/3f4 for the
195 * primary bus, and 170/374 for the secondary bus. Also, hide them
196 * from the PCI subsystem view as well so we won't try to perform
197 * our own auto-configuration on them.
199 * In addition, we ensure that the PCI IDE interrupts are routed to
200 * IRQ 14 and IRQ 15 respectively.
202 * The above gets us to a point where the IDE on this device is
203 * functional. However, The CY82C693U _does not work_ in bus
204 * master mode without locking the PCI bus solid.
206 static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
208 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
211 if (dev->class & 0x80) { /* primary */
214 } else { /* secondary */
219 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
220 base0 | PCI_BASE_ADDRESS_SPACE_IO);
221 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
222 base1 | PCI_BASE_ADDRESS_SPACE_IO);
224 dev->resource[0].start = 0;
225 dev->resource[0].end = 0;
226 dev->resource[0].flags = 0;
228 dev->resource[1].start = 0;
229 dev->resource[1].end = 0;
230 dev->resource[1].flags = 0;
231 } else if (PCI_FUNC(dev->devfn) == 0) {
233 * Setup IDE IRQ routing.
235 pci_write_config_byte(dev, 0x4b, 14);
236 pci_write_config_byte(dev, 0x4c, 15);
239 * Disable FREQACK handshake, enable USB.
241 pci_write_config_byte(dev, 0x4d, 0x41);
244 * Enable PCI retry, and PCI post-write buffer.
246 pci_write_config_byte(dev, 0x44, 0x17);
249 * Enable ISA master and DMA post write buffering.
251 pci_write_config_byte(dev, 0x45, 0x03);
254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
256 static void __init pci_fixup_it8152(struct pci_dev *dev)
259 /* fixup for ITE 8152 devices */
260 /* FIXME: add defines for class 0x68000 and 0x80103 */
261 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
262 dev->class == 0x68000 ||
263 dev->class == 0x80103) {
264 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
265 dev->resource[i].start = 0;
266 dev->resource[i].end = 0;
267 dev->resource[i].flags = 0;
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
275 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
278 printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev));
279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
283 * If the bus contains any of these devices, then we must not turn on
284 * parity checking of any kind. Currently this is CyberPro 20x0 only.
286 static inline int pdev_bad_for_parity(struct pci_dev *dev)
288 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
289 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
290 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
291 (dev->vendor == PCI_VENDOR_ID_ITE &&
292 dev->device == PCI_DEVICE_ID_ITE_8152));
297 * pcibios_fixup_bus - Called after each bus is probed,
298 * but before its children are examined.
300 void pcibios_fixup_bus(struct pci_bus *bus)
303 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
306 * Walk the devices on this bus, working out what we can
309 list_for_each_entry(dev, &bus->devices, bus_list) {
312 pci_read_config_word(dev, PCI_STATUS, &status);
315 * If any device on this bus does not support fast back
316 * to back transfers, then the bus as a whole is not able
317 * to support them. Having fast back to back transfers
318 * on saves us one PCI cycle per transaction.
320 if (!(status & PCI_STATUS_FAST_BACK))
321 features &= ~PCI_COMMAND_FAST_BACK;
323 if (pdev_bad_for_parity(dev))
324 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
326 switch (dev->class >> 8) {
327 case PCI_CLASS_BRIDGE_PCI:
328 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
329 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
330 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
331 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
334 case PCI_CLASS_BRIDGE_CARDBUS:
335 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
336 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
337 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
343 * Now walk the devices again, this time setting them up.
345 list_for_each_entry(dev, &bus->devices, bus_list) {
348 pci_read_config_word(dev, PCI_COMMAND, &cmd);
350 pci_write_config_word(dev, PCI_COMMAND, cmd);
352 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
353 L1_CACHE_BYTES >> 2);
357 * Propagate the flags to the PCI bridge.
359 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
360 if (features & PCI_COMMAND_FAST_BACK)
361 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
362 if (features & PCI_COMMAND_PARITY)
363 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
367 * Report what we did for this bus
369 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
370 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
372 #ifdef CONFIG_HOTPLUG
373 EXPORT_SYMBOL(pcibios_fixup_bus);
377 * Swizzle the device pin each time we cross a bridge.
378 * This might update pin and returns the slot number.
380 static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
382 struct pci_sys_data *sys = dev->sysdata;
383 int slot = 0, oldpin = *pin;
386 slot = sys->swizzle(dev, pin);
389 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
390 pci_name(dev), oldpin, *pin, slot);
396 * Map a slot/pin to an IRQ.
398 static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
400 struct pci_sys_data *sys = dev->sysdata;
404 irq = sys->map_irq(dev, slot, pin);
407 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
408 pci_name(dev), slot, pin, irq);
413 static void __init pcibios_init_hw(struct hw_pci *hw)
415 struct pci_sys_data *sys = NULL;
419 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
420 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
422 panic("PCI: unable to allocate sys data!");
424 #ifdef CONFIG_PCI_DOMAINS
425 sys->domain = hw->domain;
429 sys->swizzle = hw->swizzle;
430 sys->map_irq = hw->map_irq;
431 INIT_LIST_HEAD(&sys->resources);
433 ret = hw->setup(nr, sys);
436 if (list_empty(&sys->resources)) {
437 pci_add_resource_offset(&sys->resources,
438 &ioport_resource, sys->io_offset);
439 pci_add_resource_offset(&sys->resources,
440 &iomem_resource, sys->mem_offset);
443 sys->bus = hw->scan(nr, sys);
446 panic("PCI: unable to scan bus!");
448 busnr = sys->bus->subordinate + 1;
450 list_add(&sys->node, &hw->buses);
459 void __init pci_common_init(struct hw_pci *hw)
461 struct pci_sys_data *sys;
463 INIT_LIST_HEAD(&hw->buses);
465 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
472 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
474 list_for_each_entry(sys, &hw->buses, node) {
475 struct pci_bus *bus = sys->bus;
477 if (!pci_has_flag(PCI_PROBE_ONLY)) {
479 * Size the bridge windows.
481 pci_bus_size_bridges(bus);
486 pci_bus_assign_resources(bus);
491 pci_enable_bridges(bus);
495 * Tell drivers about devices found.
497 pci_bus_add_devices(bus);
501 #ifndef CONFIG_PCI_HOST_ITE8152
502 void pcibios_set_master(struct pci_dev *dev)
504 /* No special bus mastering setup handling */
508 char * __init pcibios_setup(char *str)
510 if (!strcmp(str, "debug")) {
513 } else if (!strcmp(str, "firmware")) {
514 pci_add_flags(PCI_PROBE_ONLY);
521 * From arch/i386/kernel/pci-i386.c:
523 * We need to avoid collisions with `mirrored' VGA ports
524 * and other strange ISA hardware, so we always want the
525 * addresses to be allocated in the 0x000-0x0ff region
528 * Why? Because some silly external IO cards only decode
529 * the low 10 bits of the IO address. The 0x00-0xff region
530 * is reserved for motherboard devices that decode all 16
531 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
532 * but we want to try to avoid allocating at 0x2900-0x2bff
533 * which might be mirrored at 0x0100-0x03ff..
535 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
536 resource_size_t size, resource_size_t align)
538 resource_size_t start = res->start;
540 if (res->flags & IORESOURCE_IO && start & 0x300)
541 start = (start + 0x3ff) & ~0x3ff;
543 start = (start + align - 1) & ~(align - 1);
549 * pcibios_enable_device - Enable I/O and memory.
550 * @dev: PCI device to be enabled
552 int pcibios_enable_device(struct pci_dev *dev, int mask)
558 pci_read_config_word(dev, PCI_COMMAND, &cmd);
560 for (idx = 0; idx < 6; idx++) {
561 /* Only set up the requested stuff */
562 if (!(mask & (1 << idx)))
565 r = dev->resource + idx;
566 if (!r->start && r->end) {
567 printk(KERN_ERR "PCI: Device %s not available because"
568 " of resource collisions\n", pci_name(dev));
571 if (r->flags & IORESOURCE_IO)
572 cmd |= PCI_COMMAND_IO;
573 if (r->flags & IORESOURCE_MEM)
574 cmd |= PCI_COMMAND_MEMORY;
578 * Bridges (eg, cardbus bridges) need to be fully enabled
580 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
581 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
583 if (cmd != old_cmd) {
584 printk("PCI: enabling device %s (%04x -> %04x)\n",
585 pci_name(dev), old_cmd, cmd);
586 pci_write_config_word(dev, PCI_COMMAND, cmd);
591 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
592 enum pci_mmap_state mmap_state, int write_combine)
594 struct pci_sys_data *root = dev->sysdata;
597 if (mmap_state == pci_mmap_io) {
600 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
606 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
608 if (remap_pfn_range(vma, vma->vm_start, phys,
609 vma->vm_end - vma->vm_start,