2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Low-level vector interface routines
13 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
14 * it to save wrong values... Be aware!
16 #include <linux/config.h>
19 #include <asm/vfpmacros.h>
20 #include <asm/hardware.h> @ should be moved into entry-macro.S
21 #include <asm/arch/irqs.h> @ should be moved into entry-macro.S
22 #include <asm/arch/entry-macro.S>
24 #include "entry-header.S"
27 * Invalid mode handlers
29 .macro inv_entry, sym, reason
30 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
31 stmia sp, {r0 - lr} @ Save XXX r0 - lr
37 inv_entry abt, BAD_PREFETCH
41 inv_entry abt, BAD_DATA
45 inv_entry irq, BAD_IRQ
49 inv_entry und, BAD_UNDEFINSTR
52 ldmia r4, {r5 - r7} @ Get XXX pc, cpsr, old_r0
54 stmia r4, {r5 - r7} @ Save XXX pc, cpsr, old_r0
56 and r2, r6, #31 @ int mode
63 sub sp, sp, #S_FRAME_SIZE
64 stmia sp, {r0 - r12} @ save r0 - r12
66 add r0, sp, #S_FRAME_SIZE
67 ldmia r2, {r2 - r4} @ get pc, cpsr
72 @ We are now ready to fill in the remaining blanks on the stack:
76 @ r2 - lr_<exception>, already fixed up for correct return/restart
77 @ r3 - spsr_<exception>
78 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
88 @ get ready to re-enable interrupts if appropriate
92 biceq r9, r9, #PSR_I_BIT
95 @ Call the processor-specific abort handler:
97 @ r2 - aborted context pc
98 @ r3 - aborted context cpsr
100 @ The abort handler must return the aborted address in r0, and
101 @ the fault status register in r1. r9 must be preserved.
112 @ set desired IRQ state, then call main handler
119 @ IRQs off again before pulling preserved data off the stack
124 @ restore SPSR and restart the instruction
128 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
133 #ifdef CONFIG_PREEMPT
135 ldr r9, [r8, #TI_PREEMPT] @ get preempt count
136 add r7, r9, #1 @ increment it
137 str r7, [r8, #TI_PREEMPT]
139 1: get_irqnr_and_base r0, r6, r5, lr
142 @ routine called with r0 = irq number, r1 = struct pt_regs *
146 #ifdef CONFIG_PREEMPT
147 ldr r0, [r8, #TI_FLAGS] @ get flags
148 tst r0, #_TIF_NEED_RESCHED
151 ldr r0, [r8, #TI_PREEMPT] @ read preempt value
153 str r9, [r8, #TI_PREEMPT] @ restore preempt count
154 strne r0, [r0, -r0] @ bug()
156 ldr r0, [sp, #S_PSR] @ irqs are already disabled
158 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
162 #ifdef CONFIG_PREEMPT
164 teq r9, #0 @ was preempt count = 0
165 ldreq r6, .LCirq_stat
167 ldr r0, [r6, #4] @ local_irq_count
168 ldr r1, [r6, #8] @ local_bh_count
171 mov r7, #0 @ preempt_schedule_irq
172 str r7, [r8, #TI_PREEMPT] @ expects preempt_count == 0
173 1: bl preempt_schedule_irq @ irq en/disable is done inside
174 ldr r0, [r8, #TI_FLAGS] @ get new tasks TI_FLAGS
175 tst r0, #_TIF_NEED_RESCHED
176 beq preempt_return @ go again
185 @ call emulation code, which returns using r9 if it has emulated
186 @ the instruction, or the more conventional lr if we are to treat
187 @ this as a real undefined instruction
195 mov r0, sp @ struct pt_regs *regs
199 @ IRQs off again before pulling preserved data off the stack
204 @ restore SPSR and restart the instruction
206 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
208 ldmia sp, {r0 - pc}^ @ Restore SVC registers
215 @ re-enable interrupts if appropriate
219 biceq r9, r9, #PSR_I_BIT
223 @ set args, then call main handler
225 @ r0 - address of faulting instruction
226 @ r1 - pointer to registers on stack
228 mov r0, r2 @ address (pc)
230 bl do_PrefetchAbort @ call abort handler
233 @ IRQs off again before pulling preserved data off the stack
238 @ restore SPSR and restart the instruction
242 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
257 #ifdef CONFIG_PREEMPT
265 .macro usr_entry, sym
266 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
267 stmia sp, {r0 - r12} @ save r0 - r12
270 ldmia r7, {r2 - r4} @ Get USR pc, cpsr
273 @ We are now ready to fill in the remaining blanks on the stack:
275 @ r2 - lr_<exception>, already fixed up for correct return/restart
276 @ r3 - spsr_<exception>
277 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
279 @ Also, separately save sp_usr and lr_usr
285 @ Enable the alignment trap while in kernel mode
287 alignment_trap r7, r0, __temp_\sym
290 @ Clear FP to mark the first stack frame
300 @ Call the processor-specific abort handler:
302 @ r2 - aborted context pc
303 @ r3 - aborted context cpsr
305 @ The abort handler must return the aborted address in r0, and
306 @ the fault status register in r1.
317 @ IRQs on, then call the main handler
321 adr lr, ret_from_exception
328 #ifdef CONFIG_PREEMPT
330 ldr r9, [r8, #TI_PREEMPT] @ get preempt count
331 add r7, r9, #1 @ increment it
332 str r7, [r8, #TI_PREEMPT]
334 1: get_irqnr_and_base r0, r6, r5, lr
338 @ routine called with r0 = irq number, r1 = struct pt_regs *
341 #ifdef CONFIG_PREEMPT
342 ldr r0, [r8, #TI_PREEMPT]
344 str r9, [r8, #TI_PREEMPT]
359 tst r3, #PSR_T_BIT @ Thumb mode?
360 bne fpundefinstr @ ignore FP
364 @ fall through to the emulation code, which returns using r9 if
365 @ it has emulated the instruction, or the more conventional lr
366 @ if we are to treat this as a real undefined instruction
371 adr r9, ret_from_exception
374 @ fallthrough to call_fpe
378 * The out of line fixup for the ldrt above.
380 .section .fixup, "ax"
383 .section __ex_table,"a"
388 * Check whether the instruction is a co-processor instruction.
389 * If yes, we need to call the relevant co-processor handler.
391 * Note that we don't do a full check here for the co-processor
392 * instructions; all instructions with bit 27 set are well
393 * defined. The only instructions that should fault are the
394 * co-processor instructions. However, we have to watch out
395 * for the ARM6/ARM7 SWI bug.
397 * Emulators may wish to make use of the following registers:
398 * r0 = instruction opcode.
400 * r10 = this threads thread_info structure.
403 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
404 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
405 and r8, r0, #0x0f000000 @ mask out op-code bits
406 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
409 get_thread_info r10 @ get current thread
410 and r8, r0, #0x00000f00 @ mask out CP number
412 add r6, r10, #TI_USED_CP
413 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
415 @ Test if we need to give access to iWMMXt coprocessors
416 ldr r5, [r10, #TI_FLAGS]
417 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
418 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
419 bcs iwmmxt_task_enable
422 add pc, pc, r8, lsr #6
426 b do_fpe @ CP#1 (FPE)
427 b do_fpe @ CP#2 (FPE)
436 b do_vfp @ CP#10 (VFP)
437 b do_vfp @ CP#11 (VFP)
439 mov pc, lr @ CP#10 (VFP)
440 mov pc, lr @ CP#11 (VFP)
444 mov pc, lr @ CP#14 (Debug)
445 mov pc, lr @ CP#15 (Control)
449 add r10, r10, #TI_FPSTATE @ r10 = workspace
450 ldr pc, [r4] @ Call FP module USR entry point
453 * The FP module is called with these registers set:
456 * r9 = normal "successful" return address
458 * lr = unrecognised FP instruction return address
468 adr lr, ret_from_exception
475 enable_irq @ Enable interrupts
476 mov r0, r2 @ address (pc)
478 bl do_PrefetchAbort @ call abort handler
481 * This is the return code to user mode for abort handlers
483 ENTRY(ret_from_exception)
489 * Register switch for ARMv3 and ARMv4 processors
490 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
491 * previous and next are guaranteed not to be the same.
494 add ip, r1, #TI_CPU_SAVE
495 ldr r3, [r2, #TI_TP_VALUE]
496 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
497 ldr r6, [r2, #TI_CPU_DOMAIN]!
498 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
503 str r3, [r4, #-3] @ Set TLS ptr
504 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
506 @ Always disable VFP so we can lazily save/restore the old
507 @ state. This occurs in the context of the previous thread.
509 bic r4, r4, #FPEXC_ENABLE
512 #if defined(CONFIG_IWMMXT)
513 bl iwmmxt_task_switch
514 #elif defined(CONFIG_CPU_XSCALE)
515 add r4, r2, #40 @ cpu_context_save->extra
519 ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
525 * This code is copied to 0xffff0200 so we can use branches in the
526 * vectors, rather than ldr's. Note that this code must not
527 * exceed 0x300 bytes.
529 * Common stub entry macro:
530 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
532 .macro vector_stub, name, sym, correction=0
538 sub lr, lr, #\correction
540 str lr, [r13] @ save lr_IRQ
542 str lr, [r13, #4] @ save spsr_IRQ
544 @ now branch to the relevant MODE handling routine
547 bic r13, r13, #MODE_MASK
548 orr r13, r13, #SVC_MODE
549 msr spsr_cxsf, r13 @ switch to SVC_32 mode
552 ldr lr, [pc, lr, lsl #2]
553 movs pc, lr @ Changes mode and branches
559 * Interrupt dispatcher
561 vector_stub irq, irq, 4
563 .long __irq_usr @ 0 (USR_26 / USR_32)
564 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
565 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
566 .long __irq_svc @ 3 (SVC_26 / SVC_32)
567 .long __irq_invalid @ 4
568 .long __irq_invalid @ 5
569 .long __irq_invalid @ 6
570 .long __irq_invalid @ 7
571 .long __irq_invalid @ 8
572 .long __irq_invalid @ 9
573 .long __irq_invalid @ a
574 .long __irq_invalid @ b
575 .long __irq_invalid @ c
576 .long __irq_invalid @ d
577 .long __irq_invalid @ e
578 .long __irq_invalid @ f
581 * Data abort dispatcher
582 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
584 vector_stub dabt, abt, 8
586 .long __dabt_usr @ 0 (USR_26 / USR_32)
587 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
588 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
589 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
590 .long __dabt_invalid @ 4
591 .long __dabt_invalid @ 5
592 .long __dabt_invalid @ 6
593 .long __dabt_invalid @ 7
594 .long __dabt_invalid @ 8
595 .long __dabt_invalid @ 9
596 .long __dabt_invalid @ a
597 .long __dabt_invalid @ b
598 .long __dabt_invalid @ c
599 .long __dabt_invalid @ d
600 .long __dabt_invalid @ e
601 .long __dabt_invalid @ f
604 * Prefetch abort dispatcher
605 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
607 vector_stub pabt, abt, 4
609 .long __pabt_usr @ 0 (USR_26 / USR_32)
610 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
611 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
612 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
613 .long __pabt_invalid @ 4
614 .long __pabt_invalid @ 5
615 .long __pabt_invalid @ 6
616 .long __pabt_invalid @ 7
617 .long __pabt_invalid @ 8
618 .long __pabt_invalid @ 9
619 .long __pabt_invalid @ a
620 .long __pabt_invalid @ b
621 .long __pabt_invalid @ c
622 .long __pabt_invalid @ d
623 .long __pabt_invalid @ e
624 .long __pabt_invalid @ f
627 * Undef instr entry dispatcher
628 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
632 .long __und_usr @ 0 (USR_26 / USR_32)
633 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
634 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
635 .long __und_svc @ 3 (SVC_26 / SVC_32)
636 .long __und_invalid @ 4
637 .long __und_invalid @ 5
638 .long __und_invalid @ 6
639 .long __und_invalid @ 7
640 .long __und_invalid @ 8
641 .long __und_invalid @ 9
642 .long __und_invalid @ a
643 .long __und_invalid @ b
644 .long __und_invalid @ c
645 .long __und_invalid @ d
646 .long __und_invalid @ e
647 .long __und_invalid @ f
651 /*=============================================================================
653 *-----------------------------------------------------------------------------
654 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
655 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
656 * Basically to switch modes, we *HAVE* to clobber one register... brain
657 * damage alert! I don't think that we can execute any code in here in any
658 * other mode than FIQ... Ok you can switch to another mode, but you can't
659 * get out of that mode without clobbering one register.
665 /*=============================================================================
666 * Address exception handler
667 *-----------------------------------------------------------------------------
668 * These aren't too critical.
669 * (they're not supposed to happen, and won't happen in 32-bit data mode).
676 * We group all the following data together to optimise
677 * for CPUs with separate I & D caches.
694 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
696 .globl __vectors_start
699 b vector_und + stubs_offset
700 ldr pc, .LCvswi + stubs_offset
701 b vector_pabt + stubs_offset
702 b vector_dabt + stubs_offset
703 b vector_addrexcptn + stubs_offset
704 b vector_irq + stubs_offset
705 b vector_fiq + stubs_offset
713 * Do not reorder these, and do not insert extra data between...
717 .word 0 @ saved lr_irq
718 .word 0 @ saved spsr_irq
721 .word 0 @ Saved lr_und
722 .word 0 @ Saved spsr_und
725 .word 0 @ Saved lr_abt
726 .word 0 @ Saved spsr_abt
730 .globl cr_no_alignment