2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24 #include <asm/unistd.h>
27 #include "entry-header.S"
28 #include <asm/entry-macro-multi.S>
31 * Interrupt handling. Preserves r7, r8, r9
34 #ifdef CONFIG_MULTI_IRQ_HANDLER
35 ldr r5, =handle_arch_irq
42 arch_irq_handler_default
47 .section .kprobes.text,"ax",%progbits
53 * Invalid mode handlers
55 .macro inv_entry, reason
56 sub sp, sp, #S_FRAME_SIZE
57 ARM( stmib sp, {r1 - lr} )
58 THUMB( stmia sp, {r0 - r12} )
59 THUMB( str sp, [sp, #S_SP] )
60 THUMB( str lr, [sp, #S_LR] )
65 inv_entry BAD_PREFETCH
67 ENDPROC(__pabt_invalid)
72 ENDPROC(__dabt_invalid)
77 ENDPROC(__irq_invalid)
80 inv_entry BAD_UNDEFINSTR
83 @ XXX fall through to common_invalid
87 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
93 add r0, sp, #S_PC @ here for interlock avoidance
94 mov r7, #-1 @ "" "" "" ""
95 str r4, [sp] @ save preserved r0
96 stmia r0, {r5 - r7} @ lr_<exception>,
97 @ cpsr_<exception>, "old_r0"
101 ENDPROC(__und_invalid)
107 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
108 #define SPFIX(code...) code
110 #define SPFIX(code...)
113 .macro svc_entry, stack_hole=0
115 UNWIND(.save {r0 - pc} )
116 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
117 #ifdef CONFIG_THUMB2_KERNEL
118 SPFIX( str r0, [sp] ) @ temporarily saved
120 SPFIX( tst r0, #4 ) @ test original stack alignment
121 SPFIX( ldr r0, [sp] ) @ restored
125 SPFIX( subeq sp, sp, #4 )
129 add r5, sp, #S_SP - 4 @ here for interlock avoidance
130 mov r4, #-1 @ "" "" "" ""
131 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
132 SPFIX( addeq r0, r0, #4 )
133 str r1, [sp, #-4]! @ save the "real" r0 copied
134 @ from the exception stack
139 @ We are now ready to fill in the remaining blanks on the stack:
143 @ r2 - lr_<exception>, already fixed up for correct return/restart
144 @ r3 - spsr_<exception>
145 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
155 @ get ready to re-enable interrupts if appropriate
159 biceq r9, r9, #PSR_I_BIT
162 @ Call the processor-specific abort handler:
164 @ r2 - aborted context pc
165 @ r3 - aborted context cpsr
167 @ The abort handler must return the aborted address in r0, and
168 @ the fault status register in r1. r9 must be preserved.
173 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
175 bl CPU_DABORT_HANDLER
179 @ set desired IRQ state, then call main handler
187 @ IRQs off again before pulling preserved data off the stack
192 @ restore SPSR and restart the instruction
195 svc_exit r2 @ return from exception
203 #ifdef CONFIG_TRACE_IRQFLAGS
204 bl trace_hardirqs_off
206 #ifdef CONFIG_PREEMPT
208 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
209 add r7, r8, #1 @ increment it
210 str r7, [tsk, #TI_PREEMPT]
214 #ifdef CONFIG_PREEMPT
215 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
216 ldr r0, [tsk, #TI_FLAGS] @ get flags
217 teq r8, #0 @ if preempt count != 0
218 movne r0, #0 @ force flags to 0
219 tst r0, #_TIF_NEED_RESCHED
222 ldr r4, [sp, #S_PSR] @ irqs are already disabled
223 #ifdef CONFIG_TRACE_IRQFLAGS
225 bleq trace_hardirqs_on
227 svc_exit r4 @ return from exception
233 #ifdef CONFIG_PREEMPT
236 1: bl preempt_schedule_irq @ irq en/disable is done inside
237 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
238 tst r0, #_TIF_NEED_RESCHED
239 moveq pc, r8 @ go again
245 #ifdef CONFIG_KPROBES
246 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
247 @ it obviously needs free stack space which then will belong to
255 @ call emulation code, which returns using r9 if it has emulated
256 @ the instruction, or the more conventional lr if we are to treat
257 @ this as a real undefined instruction
261 #ifndef CONFIG_THUMB2_KERNEL
264 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
266 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
267 ldrhhs r9, [r2] @ bottom 16 bits
268 orrhs r0, r9, r0, lsl #16
273 mov r0, sp @ struct pt_regs *regs
277 @ IRQs off again before pulling preserved data off the stack
279 1: disable_irq_notrace
282 @ restore SPSR and restart the instruction
284 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
285 svc_exit r2 @ return from exception
294 @ re-enable interrupts if appropriate
298 biceq r9, r9, #PSR_I_BIT
300 mov r0, r2 @ pass address of aborted instruction.
304 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
306 bl CPU_PABORT_HANDLER
309 msr cpsr_c, r9 @ Maybe enable interrupts
311 bl do_PrefetchAbort @ call abort handler
314 @ IRQs off again before pulling preserved data off the stack
319 @ restore SPSR and restart the instruction
322 svc_exit r2 @ return from exception
339 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
342 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
343 #error "sizeof(struct pt_regs) must be a multiple of 8"
348 UNWIND(.cantunwind ) @ don't unwind the user space
349 sub sp, sp, #S_FRAME_SIZE
350 ARM( stmib sp, {r1 - r12} )
351 THUMB( stmia sp, {r0 - r12} )
354 add r0, sp, #S_PC @ here for interlock avoidance
355 mov r4, #-1 @ "" "" "" ""
357 str r1, [sp] @ save the "real" r0 copied
358 @ from the exception stack
361 @ We are now ready to fill in the remaining blanks on the stack:
363 @ r2 - lr_<exception>, already fixed up for correct return/restart
364 @ r3 - spsr_<exception>
365 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
367 @ Also, separately save sp_usr and lr_usr
370 ARM( stmdb r0, {sp, lr}^ )
371 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
374 @ Enable the alignment trap while in kernel mode
379 @ Clear FP to mark the first stack frame
384 .macro kuser_cmpxchg_check
385 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
387 #warning "NPTL on non MMU needs fixing"
389 @ Make sure our user space atomic helper is restarted
390 @ if it was interrupted in a critical region. Here we
391 @ perform a quick test inline since it should be false
392 @ 99.9999% of the time. The rest is done out of line.
394 blhs kuser_cmpxchg_fixup
405 @ Call the processor-specific abort handler:
407 @ r2 - aborted context pc
408 @ r3 - aborted context cpsr
410 @ The abort handler must return the aborted address in r0, and
411 @ the fault status register in r1.
416 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
418 bl CPU_DABORT_HANDLER
422 @ IRQs on, then call the main handler
427 adr lr, BSYM(ret_from_exception)
438 #ifdef CONFIG_PREEMPT
439 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
440 add r7, r8, #1 @ increment it
441 str r7, [tsk, #TI_PREEMPT]
445 #ifdef CONFIG_PREEMPT
446 ldr r0, [tsk, #TI_PREEMPT]
447 str r8, [tsk, #TI_PREEMPT]
449 ARM( strne r0, [r0, -r0] )
450 THUMB( movne r0, #0 )
451 THUMB( strne r0, [r0] )
466 @ fall through to the emulation code, which returns using r9 if
467 @ it has emulated the instruction, or the more conventional lr
468 @ if we are to treat this as a real undefined instruction
472 adr r9, BSYM(ret_from_exception)
473 adr lr, BSYM(__und_usr_unknown)
474 tst r3, #PSR_T_BIT @ Thumb mode?
475 itet eq @ explicit IT needed for the 1f label
476 subeq r4, r2, #4 @ ARM instr at LR - 4
477 subne r4, r2, #2 @ Thumb instr at LR - 2
479 #ifdef CONFIG_CPU_ENDIAN_BE8
480 reveq r0, r0 @ little endian instruction
484 #if __LINUX_ARM_ARCH__ >= 7
486 ARM( ldrht r5, [r4], #2 )
487 THUMB( ldrht r5, [r4] )
488 THUMB( add r4, r4, #2 )
489 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
490 cmp r0, #0xe800 @ 32bit instruction if xx != 0
491 blo __und_usr_unknown
493 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
494 orr r0, r0, r5, lsl #16
502 @ fallthrough to call_fpe
506 * The out of line fixup for the ldrt above.
508 .pushsection .fixup, "ax"
511 .pushsection __ex_table,"a"
513 #if __LINUX_ARM_ARCH__ >= 7
520 * Check whether the instruction is a co-processor instruction.
521 * If yes, we need to call the relevant co-processor handler.
523 * Note that we don't do a full check here for the co-processor
524 * instructions; all instructions with bit 27 set are well
525 * defined. The only instructions that should fault are the
526 * co-processor instructions. However, we have to watch out
527 * for the ARM6/ARM7 SWI bug.
529 * NEON is a special case that has to be handled here. Not all
530 * NEON instructions are co-processor instructions, so we have
531 * to make a special case of checking for them. Plus, there's
532 * five groups of them, so we have a table of mask/opcode pairs
533 * to check against, and if any match then we branch off into the
536 * Emulators may wish to make use of the following registers:
537 * r0 = instruction opcode.
539 * r9 = normal "successful" return address
540 * r10 = this threads thread_info structure.
541 * lr = unrecognised instruction return address
544 @ Fall-through from Thumb-2 __und_usr
547 adr r6, .LCneon_thumb_opcodes
552 adr r6, .LCneon_arm_opcodes
554 ldr r7, [r6], #4 @ mask value
555 cmp r7, #0 @ end mask?
558 ldr r7, [r6], #4 @ opcode bits matching in mask
559 cmp r8, r7 @ NEON instruction?
563 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
564 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
565 b do_vfp @ let VFP handler handle this
568 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
569 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
570 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
571 and r8, r0, #0x0f000000 @ mask out op-code bits
572 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
575 get_thread_info r10 @ get current thread
576 and r8, r0, #0x00000f00 @ mask out CP number
577 THUMB( lsr r8, r8, #8 )
579 add r6, r10, #TI_USED_CP
580 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
581 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
583 @ Test if we need to give access to iWMMXt coprocessors
584 ldr r5, [r10, #TI_FLAGS]
585 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
586 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
587 bcs iwmmxt_task_enable
589 ARM( add pc, pc, r8, lsr #6 )
590 THUMB( lsl r8, r8, #2 )
595 W(b) do_fpe @ CP#1 (FPE)
596 W(b) do_fpe @ CP#2 (FPE)
599 b crunch_task_enable @ CP#4 (MaverickCrunch)
600 b crunch_task_enable @ CP#5 (MaverickCrunch)
601 b crunch_task_enable @ CP#6 (MaverickCrunch)
611 W(b) do_vfp @ CP#10 (VFP)
612 W(b) do_vfp @ CP#11 (VFP)
614 movw_pc lr @ CP#10 (VFP)
615 movw_pc lr @ CP#11 (VFP)
619 movw_pc lr @ CP#14 (Debug)
620 movw_pc lr @ CP#15 (Control)
626 .word 0xfe000000 @ mask
627 .word 0xf2000000 @ opcode
629 .word 0xff100000 @ mask
630 .word 0xf4000000 @ opcode
632 .word 0x00000000 @ mask
633 .word 0x00000000 @ opcode
635 .LCneon_thumb_opcodes:
636 .word 0xef000000 @ mask
637 .word 0xef000000 @ opcode
639 .word 0xff100000 @ mask
640 .word 0xf9000000 @ opcode
642 .word 0x00000000 @ mask
643 .word 0x00000000 @ opcode
649 add r10, r10, #TI_FPSTATE @ r10 = workspace
650 ldr pc, [r4] @ Call FP module USR entry point
653 * The FP module is called with these registers set:
656 * r9 = normal "successful" return address
658 * lr = unrecognised FP instruction return address
673 adr lr, BSYM(ret_from_exception)
675 ENDPROC(__und_usr_unknown)
681 mov r0, r2 @ pass address of aborted instruction.
685 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
687 bl CPU_PABORT_HANDLER
690 enable_irq @ Enable interrupts
692 bl do_PrefetchAbort @ call abort handler
696 * This is the return code to user mode for abort handlers
698 ENTRY(ret_from_exception)
706 ENDPROC(ret_from_exception)
709 * Register switch for ARMv3 and ARMv4 processors
710 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
711 * previous and next are guaranteed not to be the same.
716 add ip, r1, #TI_CPU_SAVE
717 ldr r3, [r2, #TI_TP_VALUE]
718 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
719 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
720 THUMB( str sp, [ip], #4 )
721 THUMB( str lr, [ip], #4 )
722 #ifdef CONFIG_CPU_USE_DOMAINS
723 ldr r6, [r2, #TI_CPU_DOMAIN]
726 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
727 ldr r7, [r2, #TI_TASK]
728 ldr r8, =__stack_chk_guard
729 ldr r7, [r7, #TSK_STACK_CANARY]
731 #ifdef CONFIG_CPU_USE_DOMAINS
732 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
735 add r4, r2, #TI_CPU_SAVE
736 ldr r0, =thread_notify_head
737 mov r1, #THREAD_NOTIFY_SWITCH
738 bl atomic_notifier_call_chain
739 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
744 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
745 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
746 THUMB( ldr sp, [ip], #4 )
747 THUMB( ldr pc, [ip] )
756 * These are segment of kernel provided user code reachable from user space
757 * at a fixed address in kernel memory. This is used to provide user space
758 * with some operations which require kernel help because of unimplemented
759 * native feature and/or instructions in many ARM CPUs. The idea is for
760 * this code to be executed directly in user mode for best efficiency but
761 * which is too intimate with the kernel counter part to be left to user
762 * libraries. In fact this code might even differ from one CPU to another
763 * depending on the available instruction set and restrictions like on
764 * SMP systems. In other words, the kernel reserves the right to change
765 * this code as needed without warning. Only the entry points and their
766 * results are guaranteed to be stable.
768 * Each segment is 32-byte aligned and will be moved to the top of the high
769 * vector page. New segments (if ever needed) must be added in front of
770 * existing ones. This mechanism should be used only for things that are
771 * really small and justified, and not be abused freely.
773 * User space is expected to implement those things inline when optimizing
774 * for a processor that has the necessary native support, but only if such
775 * resulting binaries are already to be incompatible with earlier ARM
776 * processors due to the use of unsupported instructions other than what
777 * is provided here. In other words don't make binaries unable to run on
778 * earlier processors just for the sake of not using these kernel helpers
779 * if your compiled code is not going to use the new instructions for other
785 #ifdef CONFIG_ARM_THUMB
793 .globl __kuser_helper_start
794 __kuser_helper_start:
797 * Reference prototype:
799 * void __kernel_memory_barrier(void)
803 * lr = return address
813 * Definition and user space usage example:
815 * typedef void (__kernel_dmb_t)(void);
816 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
818 * Apply any needed memory barrier to preserve consistency with data modified
819 * manually and __kuser_cmpxchg usage.
821 * This could be used as follows:
823 * #define __kernel_dmb() \
824 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
825 * : : : "r0", "lr","cc" )
828 __kuser_memory_barrier: @ 0xffff0fa0
835 * Reference prototype:
837 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
844 * lr = return address
848 * r0 = returned value (zero or non-zero)
849 * C flag = set if r0 == 0, clear if r0 != 0
855 * Definition and user space usage example:
857 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
858 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
860 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
861 * Return zero if *ptr was changed or non-zero if no exchange happened.
862 * The C flag is also set if *ptr was changed to allow for assembly
863 * optimization in the calling code.
867 * - This routine already includes memory barriers as needed.
869 * For example, a user space atomic_add implementation could look like this:
871 * #define atomic_add(ptr, val) \
872 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
873 * register unsigned int __result asm("r1"); \
875 * "1: @ atomic_add\n\t" \
876 * "ldr r0, [r2]\n\t" \
877 * "mov r3, #0xffff0fff\n\t" \
878 * "add lr, pc, #4\n\t" \
879 * "add r1, r0, %2\n\t" \
880 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
882 * : "=&r" (__result) \
883 * : "r" (__ptr), "rIL" (val) \
884 * : "r0","r3","ip","lr","cc","memory" ); \
888 __kuser_cmpxchg: @ 0xffff0fc0
890 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
893 * Poor you. No fast solution possible...
894 * The kernel itself must perform the operation.
895 * A special ghost syscall is used for that (see traps.c).
898 ldr r7, 1f @ it's 20 bits
901 1: .word __ARM_NR_cmpxchg
903 #elif __LINUX_ARM_ARCH__ < 6
908 * The only thing that can break atomicity in this cmpxchg
909 * implementation is either an IRQ or a data abort exception
910 * causing another process/thread to be scheduled in the middle
911 * of the critical sequence. To prevent this, code is added to
912 * the IRQ and data abort exception handlers to set the pc back
913 * to the beginning of the critical section if it is found to be
914 * within that critical section (see kuser_cmpxchg_fixup).
916 1: ldr r3, [r2] @ load current val
917 subs r3, r3, r0 @ compare with oldval
918 2: streq r1, [r2] @ store newval if eq
919 rsbs r0, r3, #0 @ set return val and C flag
924 @ Called from kuser_cmpxchg_check macro.
925 @ r2 = address of interrupted insn (must be preserved).
926 @ sp = saved regs. r7 and r8 are clobbered.
927 @ 1b = first critical insn, 2b = last critical insn.
928 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
930 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
932 rsbcss r8, r8, #(2b - 1b)
933 strcs r7, [sp, #S_PC]
938 #warning "NPTL on non MMU needs fixing"
953 /* beware -- each __kuser slot must be 8 instructions max */
954 ALT_SMP(b __kuser_memory_barrier)
962 * Reference prototype:
964 * int __kernel_get_tls(void)
968 * lr = return address
978 * Definition and user space usage example:
980 * typedef int (__kernel_get_tls_t)(void);
981 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
983 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
985 * This could be used as follows:
987 * #define __kernel_get_tls() \
988 * ({ register unsigned int __val asm("r0"); \
989 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
990 * : "=r" (__val) : : "lr","cc" ); \
994 __kuser_get_tls: @ 0xffff0fe0
995 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
997 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
999 .word 0 @ 0xffff0ff0 software TLS value, then
1000 .endr @ pad up to __kuser_helper_version
1003 * Reference declaration:
1005 * extern unsigned int __kernel_helper_version;
1007 * Definition and user space usage example:
1009 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1011 * User space may read this to determine the curent number of helpers
1015 __kuser_helper_version: @ 0xffff0ffc
1016 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1018 .globl __kuser_helper_end
1026 * This code is copied to 0xffff0200 so we can use branches in the
1027 * vectors, rather than ldr's. Note that this code must not
1028 * exceed 0x300 bytes.
1030 * Common stub entry macro:
1031 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1033 * SP points to a minimal amount of processor-private memory, the address
1034 * of which is copied into r0 for the mode specific abort handler.
1036 .macro vector_stub, name, mode, correction=0
1041 sub lr, lr, #\correction
1045 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1048 stmia sp, {r0, lr} @ save r0, lr
1050 str lr, [sp, #8] @ save spsr
1053 @ Prepare for SVC32 mode. IRQs remain disabled.
1056 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1060 @ the branch table must immediately follow this code
1064 THUMB( ldr lr, [r0, lr, lsl #2] )
1066 ARM( ldr lr, [pc, lr, lsl #2] )
1067 movs pc, lr @ branch to handler in SVC mode
1068 ENDPROC(vector_\name)
1071 @ handler addresses follow this label
1075 .globl __stubs_start
1078 * Interrupt dispatcher
1080 vector_stub irq, IRQ_MODE, 4
1082 .long __irq_usr @ 0 (USR_26 / USR_32)
1083 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1084 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1085 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1086 .long __irq_invalid @ 4
1087 .long __irq_invalid @ 5
1088 .long __irq_invalid @ 6
1089 .long __irq_invalid @ 7
1090 .long __irq_invalid @ 8
1091 .long __irq_invalid @ 9
1092 .long __irq_invalid @ a
1093 .long __irq_invalid @ b
1094 .long __irq_invalid @ c
1095 .long __irq_invalid @ d
1096 .long __irq_invalid @ e
1097 .long __irq_invalid @ f
1100 * Data abort dispatcher
1101 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1103 vector_stub dabt, ABT_MODE, 8
1105 .long __dabt_usr @ 0 (USR_26 / USR_32)
1106 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1107 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1108 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1109 .long __dabt_invalid @ 4
1110 .long __dabt_invalid @ 5
1111 .long __dabt_invalid @ 6
1112 .long __dabt_invalid @ 7
1113 .long __dabt_invalid @ 8
1114 .long __dabt_invalid @ 9
1115 .long __dabt_invalid @ a
1116 .long __dabt_invalid @ b
1117 .long __dabt_invalid @ c
1118 .long __dabt_invalid @ d
1119 .long __dabt_invalid @ e
1120 .long __dabt_invalid @ f
1123 * Prefetch abort dispatcher
1124 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1126 vector_stub pabt, ABT_MODE, 4
1128 .long __pabt_usr @ 0 (USR_26 / USR_32)
1129 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1130 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1131 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1132 .long __pabt_invalid @ 4
1133 .long __pabt_invalid @ 5
1134 .long __pabt_invalid @ 6
1135 .long __pabt_invalid @ 7
1136 .long __pabt_invalid @ 8
1137 .long __pabt_invalid @ 9
1138 .long __pabt_invalid @ a
1139 .long __pabt_invalid @ b
1140 .long __pabt_invalid @ c
1141 .long __pabt_invalid @ d
1142 .long __pabt_invalid @ e
1143 .long __pabt_invalid @ f
1146 * Undef instr entry dispatcher
1147 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1149 vector_stub und, UND_MODE
1151 .long __und_usr @ 0 (USR_26 / USR_32)
1152 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1153 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1154 .long __und_svc @ 3 (SVC_26 / SVC_32)
1155 .long __und_invalid @ 4
1156 .long __und_invalid @ 5
1157 .long __und_invalid @ 6
1158 .long __und_invalid @ 7
1159 .long __und_invalid @ 8
1160 .long __und_invalid @ 9
1161 .long __und_invalid @ a
1162 .long __und_invalid @ b
1163 .long __und_invalid @ c
1164 .long __und_invalid @ d
1165 .long __und_invalid @ e
1166 .long __und_invalid @ f
1170 /*=============================================================================
1172 *-----------------------------------------------------------------------------
1173 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1174 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1175 * Basically to switch modes, we *HAVE* to clobber one register... brain
1176 * damage alert! I don't think that we can execute any code in here in any
1177 * other mode than FIQ... Ok you can switch to another mode, but you can't
1178 * get out of that mode without clobbering one register.
1184 /*=============================================================================
1185 * Address exception handler
1186 *-----------------------------------------------------------------------------
1187 * These aren't too critical.
1188 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1195 * We group all the following data together to optimise
1196 * for CPUs with separate I & D caches.
1206 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1208 .globl __vectors_start
1210 ARM( swi SYS_ERROR0 )
1213 W(b) vector_und + stubs_offset
1214 W(ldr) pc, .LCvswi + stubs_offset
1215 W(b) vector_pabt + stubs_offset
1216 W(b) vector_dabt + stubs_offset
1217 W(b) vector_addrexcptn + stubs_offset
1218 W(b) vector_irq + stubs_offset
1219 W(b) vector_fiq + stubs_offset
1221 .globl __vectors_end
1227 .globl cr_no_alignment
1233 #ifdef CONFIG_MULTI_IRQ_HANDLER
1234 .globl handle_arch_irq