2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24 #include <asm/unistd.h>
26 #include "entry-header.S"
29 * Interrupt handling. Preserves r7, r8, r9
32 get_irqnr_preamble r5, lr
33 1: get_irqnr_and_base r0, r6, r5, lr
36 @ routine called with r0 = irq number, r1 = struct pt_regs *
45 * this macro assumes that irqstat (r6) and base (r5) are
46 * preserved from get_irqnr_and_base above
48 test_for_ipi r0, r6, r5, lr
53 #ifdef CONFIG_LOCAL_TIMERS
54 test_for_ltirq r0, r6, r5, lr
64 .section .kprobes.text,"ax",%progbits
70 * Invalid mode handlers
72 .macro inv_entry, reason
73 sub sp, sp, #S_FRAME_SIZE
74 ARM( stmib sp, {r1 - lr} )
75 THUMB( stmia sp, {r0 - r12} )
76 THUMB( str sp, [sp, #S_SP] )
77 THUMB( str lr, [sp, #S_LR] )
82 inv_entry BAD_PREFETCH
84 ENDPROC(__pabt_invalid)
89 ENDPROC(__dabt_invalid)
94 ENDPROC(__irq_invalid)
97 inv_entry BAD_UNDEFINSTR
100 @ XXX fall through to common_invalid
104 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
110 add r0, sp, #S_PC @ here for interlock avoidance
111 mov r7, #-1 @ "" "" "" ""
112 str r4, [sp] @ save preserved r0
113 stmia r0, {r5 - r7} @ lr_<exception>,
114 @ cpsr_<exception>, "old_r0"
118 ENDPROC(__und_invalid)
124 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
125 #define SPFIX(code...) code
127 #define SPFIX(code...)
130 .macro svc_entry, stack_hole=0
132 UNWIND(.save {r0 - pc} )
133 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
134 #ifdef CONFIG_THUMB2_KERNEL
135 SPFIX( str r0, [sp] ) @ temporarily saved
137 SPFIX( tst r0, #4 ) @ test original stack alignment
138 SPFIX( ldr r0, [sp] ) @ restored
142 SPFIX( subeq sp, sp, #4 )
146 add r5, sp, #S_SP - 4 @ here for interlock avoidance
147 mov r4, #-1 @ "" "" "" ""
148 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
149 SPFIX( addeq r0, r0, #4 )
150 str r1, [sp, #-4]! @ save the "real" r0 copied
151 @ from the exception stack
156 @ We are now ready to fill in the remaining blanks on the stack:
160 @ r2 - lr_<exception>, already fixed up for correct return/restart
161 @ r3 - spsr_<exception>
162 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
172 @ get ready to re-enable interrupts if appropriate
176 biceq r9, r9, #PSR_I_BIT
179 @ Call the processor-specific abort handler:
181 @ r2 - aborted context pc
182 @ r3 - aborted context cpsr
184 @ The abort handler must return the aborted address in r0, and
185 @ the fault status register in r1. r9 must be preserved.
190 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
192 bl CPU_DABORT_HANDLER
196 @ set desired IRQ state, then call main handler
203 @ IRQs off again before pulling preserved data off the stack
208 @ restore SPSR and restart the instruction
211 svc_exit r2 @ return from exception
219 #ifdef CONFIG_TRACE_IRQFLAGS
220 bl trace_hardirqs_off
222 #ifdef CONFIG_PREEMPT
224 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
225 add r7, r8, #1 @ increment it
226 str r7, [tsk, #TI_PREEMPT]
230 #ifdef CONFIG_PREEMPT
231 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
232 ldr r0, [tsk, #TI_FLAGS] @ get flags
233 teq r8, #0 @ if preempt count != 0
234 movne r0, #0 @ force flags to 0
235 tst r0, #_TIF_NEED_RESCHED
238 ldr r4, [sp, #S_PSR] @ irqs are already disabled
239 #ifdef CONFIG_TRACE_IRQFLAGS
241 bleq trace_hardirqs_on
243 svc_exit r4 @ return from exception
249 #ifdef CONFIG_PREEMPT
252 1: bl preempt_schedule_irq @ irq en/disable is done inside
253 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
254 tst r0, #_TIF_NEED_RESCHED
255 moveq pc, r8 @ go again
261 #ifdef CONFIG_KPROBES
262 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
263 @ it obviously needs free stack space which then will belong to
271 @ call emulation code, which returns using r9 if it has emulated
272 @ the instruction, or the more conventional lr if we are to treat
273 @ this as a real undefined instruction
277 #ifndef CONFIG_THUMB2_KERNEL
280 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
282 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
283 ldrhhs r9, [r2] @ bottom 16 bits
284 orrhs r0, r9, r0, lsl #16
289 mov r0, sp @ struct pt_regs *regs
293 @ IRQs off again before pulling preserved data off the stack
295 1: disable_irq_notrace
298 @ restore SPSR and restart the instruction
300 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
301 svc_exit r2 @ return from exception
310 @ re-enable interrupts if appropriate
314 biceq r9, r9, #PSR_I_BIT
316 mov r0, r2 @ pass address of aborted instruction.
320 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
322 bl CPU_PABORT_HANDLER
324 msr cpsr_c, r9 @ Maybe enable interrupts
326 bl do_PrefetchAbort @ call abort handler
329 @ IRQs off again before pulling preserved data off the stack
334 @ restore SPSR and restart the instruction
337 svc_exit r2 @ return from exception
354 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
357 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
358 #error "sizeof(struct pt_regs) must be a multiple of 8"
363 UNWIND(.cantunwind ) @ don't unwind the user space
364 sub sp, sp, #S_FRAME_SIZE
365 ARM( stmib sp, {r1 - r12} )
366 THUMB( stmia sp, {r0 - r12} )
369 add r0, sp, #S_PC @ here for interlock avoidance
370 mov r4, #-1 @ "" "" "" ""
372 str r1, [sp] @ save the "real" r0 copied
373 @ from the exception stack
376 @ We are now ready to fill in the remaining blanks on the stack:
378 @ r2 - lr_<exception>, already fixed up for correct return/restart
379 @ r3 - spsr_<exception>
380 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
382 @ Also, separately save sp_usr and lr_usr
385 ARM( stmdb r0, {sp, lr}^ )
386 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
389 @ Enable the alignment trap while in kernel mode
394 @ Clear FP to mark the first stack frame
399 .macro kuser_cmpxchg_check
400 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
402 #warning "NPTL on non MMU needs fixing"
404 @ Make sure our user space atomic helper is restarted
405 @ if it was interrupted in a critical region. Here we
406 @ perform a quick test inline since it should be false
407 @ 99.9999% of the time. The rest is done out of line.
409 blhs kuser_cmpxchg_fixup
420 @ Call the processor-specific abort handler:
422 @ r2 - aborted context pc
423 @ r3 - aborted context cpsr
425 @ The abort handler must return the aborted address in r0, and
426 @ the fault status register in r1.
431 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
433 bl CPU_DABORT_HANDLER
437 @ IRQs on, then call the main handler
441 adr lr, BSYM(ret_from_exception)
452 #ifdef CONFIG_PREEMPT
453 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
454 add r7, r8, #1 @ increment it
455 str r7, [tsk, #TI_PREEMPT]
459 #ifdef CONFIG_PREEMPT
460 ldr r0, [tsk, #TI_PREEMPT]
461 str r8, [tsk, #TI_PREEMPT]
463 ARM( strne r0, [r0, -r0] )
464 THUMB( movne r0, #0 )
465 THUMB( strne r0, [r0] )
480 @ fall through to the emulation code, which returns using r9 if
481 @ it has emulated the instruction, or the more conventional lr
482 @ if we are to treat this as a real undefined instruction
486 adr r9, BSYM(ret_from_exception)
487 adr lr, BSYM(__und_usr_unknown)
488 tst r3, #PSR_T_BIT @ Thumb mode?
489 itet eq @ explicit IT needed for the 1f label
490 subeq r4, r2, #4 @ ARM instr at LR - 4
491 subne r4, r2, #2 @ Thumb instr at LR - 2
493 #ifdef CONFIG_CPU_ENDIAN_BE8
494 reveq r0, r0 @ little endian instruction
498 #if __LINUX_ARM_ARCH__ >= 7
500 ARM( ldrht r5, [r4], #2 )
501 THUMB( ldrht r5, [r4] )
502 THUMB( add r4, r4, #2 )
503 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
504 cmp r0, #0xe800 @ 32bit instruction if xx != 0
505 blo __und_usr_unknown
507 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
508 orr r0, r0, r5, lsl #16
516 @ fallthrough to call_fpe
520 * The out of line fixup for the ldrt above.
522 .pushsection .fixup, "ax"
525 .pushsection __ex_table,"a"
527 #if __LINUX_ARM_ARCH__ >= 7
534 * Check whether the instruction is a co-processor instruction.
535 * If yes, we need to call the relevant co-processor handler.
537 * Note that we don't do a full check here for the co-processor
538 * instructions; all instructions with bit 27 set are well
539 * defined. The only instructions that should fault are the
540 * co-processor instructions. However, we have to watch out
541 * for the ARM6/ARM7 SWI bug.
543 * NEON is a special case that has to be handled here. Not all
544 * NEON instructions are co-processor instructions, so we have
545 * to make a special case of checking for them. Plus, there's
546 * five groups of them, so we have a table of mask/opcode pairs
547 * to check against, and if any match then we branch off into the
550 * Emulators may wish to make use of the following registers:
551 * r0 = instruction opcode.
553 * r9 = normal "successful" return address
554 * r10 = this threads thread_info structure.
555 * lr = unrecognised instruction return address
558 @ Fall-through from Thumb-2 __und_usr
561 adr r6, .LCneon_thumb_opcodes
566 adr r6, .LCneon_arm_opcodes
568 ldr r7, [r6], #4 @ mask value
569 cmp r7, #0 @ end mask?
572 ldr r7, [r6], #4 @ opcode bits matching in mask
573 cmp r8, r7 @ NEON instruction?
577 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
578 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
579 b do_vfp @ let VFP handler handle this
582 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
583 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
584 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
585 and r8, r0, #0x0f000000 @ mask out op-code bits
586 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
589 get_thread_info r10 @ get current thread
590 and r8, r0, #0x00000f00 @ mask out CP number
591 THUMB( lsr r8, r8, #8 )
593 add r6, r10, #TI_USED_CP
594 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
595 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
597 @ Test if we need to give access to iWMMXt coprocessors
598 ldr r5, [r10, #TI_FLAGS]
599 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
600 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
601 bcs iwmmxt_task_enable
603 ARM( add pc, pc, r8, lsr #6 )
604 THUMB( lsl r8, r8, #2 )
609 W(b) do_fpe @ CP#1 (FPE)
610 W(b) do_fpe @ CP#2 (FPE)
613 b crunch_task_enable @ CP#4 (MaverickCrunch)
614 b crunch_task_enable @ CP#5 (MaverickCrunch)
615 b crunch_task_enable @ CP#6 (MaverickCrunch)
625 W(b) do_vfp @ CP#10 (VFP)
626 W(b) do_vfp @ CP#11 (VFP)
628 movw_pc lr @ CP#10 (VFP)
629 movw_pc lr @ CP#11 (VFP)
633 movw_pc lr @ CP#14 (Debug)
634 movw_pc lr @ CP#15 (Control)
640 .word 0xfe000000 @ mask
641 .word 0xf2000000 @ opcode
643 .word 0xff100000 @ mask
644 .word 0xf4000000 @ opcode
646 .word 0x00000000 @ mask
647 .word 0x00000000 @ opcode
649 .LCneon_thumb_opcodes:
650 .word 0xef000000 @ mask
651 .word 0xef000000 @ opcode
653 .word 0xff100000 @ mask
654 .word 0xf9000000 @ opcode
656 .word 0x00000000 @ mask
657 .word 0x00000000 @ opcode
663 add r10, r10, #TI_FPSTATE @ r10 = workspace
664 ldr pc, [r4] @ Call FP module USR entry point
667 * The FP module is called with these registers set:
670 * r9 = normal "successful" return address
672 * lr = unrecognised FP instruction return address
687 adr lr, BSYM(ret_from_exception)
689 ENDPROC(__und_usr_unknown)
695 mov r0, r2 @ pass address of aborted instruction.
699 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
701 bl CPU_PABORT_HANDLER
703 enable_irq @ Enable interrupts
705 bl do_PrefetchAbort @ call abort handler
709 * This is the return code to user mode for abort handlers
711 ENTRY(ret_from_exception)
719 ENDPROC(ret_from_exception)
722 * Register switch for ARMv3 and ARMv4 processors
723 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
724 * previous and next are guaranteed not to be the same.
729 add ip, r1, #TI_CPU_SAVE
730 ldr r3, [r2, #TI_TP_VALUE]
731 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
732 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
733 THUMB( str sp, [ip], #4 )
734 THUMB( str lr, [ip], #4 )
736 ldr r6, [r2, #TI_CPU_DOMAIN]
738 #if defined(CONFIG_HAS_TLS_REG)
739 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
740 #elif !defined(CONFIG_TLS_REG_EMUL)
742 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
745 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
748 add r4, r2, #TI_CPU_SAVE
749 ldr r0, =thread_notify_head
750 mov r1, #THREAD_NOTIFY_SWITCH
751 bl atomic_notifier_call_chain
754 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
755 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
756 THUMB( ldr sp, [ip], #4 )
757 THUMB( ldr pc, [ip] )
766 * These are segment of kernel provided user code reachable from user space
767 * at a fixed address in kernel memory. This is used to provide user space
768 * with some operations which require kernel help because of unimplemented
769 * native feature and/or instructions in many ARM CPUs. The idea is for
770 * this code to be executed directly in user mode for best efficiency but
771 * which is too intimate with the kernel counter part to be left to user
772 * libraries. In fact this code might even differ from one CPU to another
773 * depending on the available instruction set and restrictions like on
774 * SMP systems. In other words, the kernel reserves the right to change
775 * this code as needed without warning. Only the entry points and their
776 * results are guaranteed to be stable.
778 * Each segment is 32-byte aligned and will be moved to the top of the high
779 * vector page. New segments (if ever needed) must be added in front of
780 * existing ones. This mechanism should be used only for things that are
781 * really small and justified, and not be abused freely.
783 * User space is expected to implement those things inline when optimizing
784 * for a processor that has the necessary native support, but only if such
785 * resulting binaries are already to be incompatible with earlier ARM
786 * processors due to the use of unsupported instructions other than what
787 * is provided here. In other words don't make binaries unable to run on
788 * earlier processors just for the sake of not using these kernel helpers
789 * if your compiled code is not going to use the new instructions for other
795 #ifdef CONFIG_ARM_THUMB
803 .globl __kuser_helper_start
804 __kuser_helper_start:
807 * Reference prototype:
809 * void __kernel_memory_barrier(void)
813 * lr = return address
823 * Definition and user space usage example:
825 * typedef void (__kernel_dmb_t)(void);
826 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
828 * Apply any needed memory barrier to preserve consistency with data modified
829 * manually and __kuser_cmpxchg usage.
831 * This could be used as follows:
833 * #define __kernel_dmb() \
834 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
835 * : : : "r0", "lr","cc" )
838 __kuser_memory_barrier: @ 0xffff0fa0
845 * Reference prototype:
847 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
854 * lr = return address
858 * r0 = returned value (zero or non-zero)
859 * C flag = set if r0 == 0, clear if r0 != 0
865 * Definition and user space usage example:
867 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
868 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
870 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
871 * Return zero if *ptr was changed or non-zero if no exchange happened.
872 * The C flag is also set if *ptr was changed to allow for assembly
873 * optimization in the calling code.
877 * - This routine already includes memory barriers as needed.
879 * For example, a user space atomic_add implementation could look like this:
881 * #define atomic_add(ptr, val) \
882 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
883 * register unsigned int __result asm("r1"); \
885 * "1: @ atomic_add\n\t" \
886 * "ldr r0, [r2]\n\t" \
887 * "mov r3, #0xffff0fff\n\t" \
888 * "add lr, pc, #4\n\t" \
889 * "add r1, r0, %2\n\t" \
890 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
892 * : "=&r" (__result) \
893 * : "r" (__ptr), "rIL" (val) \
894 * : "r0","r3","ip","lr","cc","memory" ); \
898 __kuser_cmpxchg: @ 0xffff0fc0
900 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
903 * Poor you. No fast solution possible...
904 * The kernel itself must perform the operation.
905 * A special ghost syscall is used for that (see traps.c).
908 ldr r7, =1f @ it's 20 bits
911 1: .word __ARM_NR_cmpxchg
913 #elif __LINUX_ARM_ARCH__ < 6
918 * The only thing that can break atomicity in this cmpxchg
919 * implementation is either an IRQ or a data abort exception
920 * causing another process/thread to be scheduled in the middle
921 * of the critical sequence. To prevent this, code is added to
922 * the IRQ and data abort exception handlers to set the pc back
923 * to the beginning of the critical section if it is found to be
924 * within that critical section (see kuser_cmpxchg_fixup).
926 1: ldr r3, [r2] @ load current val
927 subs r3, r3, r0 @ compare with oldval
928 2: streq r1, [r2] @ store newval if eq
929 rsbs r0, r3, #0 @ set return val and C flag
934 @ Called from kuser_cmpxchg_check macro.
935 @ r2 = address of interrupted insn (must be preserved).
936 @ sp = saved regs. r7 and r8 are clobbered.
937 @ 1b = first critical insn, 2b = last critical insn.
938 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
940 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
942 rsbcss r8, r8, #(2b - 1b)
943 strcs r7, [sp, #S_PC]
948 #warning "NPTL on non MMU needs fixing"
963 /* beware -- each __kuser slot must be 8 instructions max */
965 b __kuser_memory_barrier
975 * Reference prototype:
977 * int __kernel_get_tls(void)
981 * lr = return address
991 * Definition and user space usage example:
993 * typedef int (__kernel_get_tls_t)(void);
994 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
996 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
998 * This could be used as follows:
1000 * #define __kernel_get_tls() \
1001 * ({ register unsigned int __val asm("r0"); \
1002 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1003 * : "=r" (__val) : : "lr","cc" ); \
1007 __kuser_get_tls: @ 0xffff0fe0
1009 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1010 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1012 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1017 .word 0 @ pad up to __kuser_helper_version
1021 * Reference declaration:
1023 * extern unsigned int __kernel_helper_version;
1025 * Definition and user space usage example:
1027 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1029 * User space may read this to determine the curent number of helpers
1033 __kuser_helper_version: @ 0xffff0ffc
1034 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1036 .globl __kuser_helper_end
1044 * This code is copied to 0xffff0200 so we can use branches in the
1045 * vectors, rather than ldr's. Note that this code must not
1046 * exceed 0x300 bytes.
1048 * Common stub entry macro:
1049 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1051 * SP points to a minimal amount of processor-private memory, the address
1052 * of which is copied into r0 for the mode specific abort handler.
1054 .macro vector_stub, name, mode, correction=0
1059 sub lr, lr, #\correction
1063 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1066 stmia sp, {r0, lr} @ save r0, lr
1068 str lr, [sp, #8] @ save spsr
1071 @ Prepare for SVC32 mode. IRQs remain disabled.
1074 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1078 @ the branch table must immediately follow this code
1082 THUMB( ldr lr, [r0, lr, lsl #2] )
1084 ARM( ldr lr, [pc, lr, lsl #2] )
1085 movs pc, lr @ branch to handler in SVC mode
1086 ENDPROC(vector_\name)
1089 @ handler addresses follow this label
1093 .globl __stubs_start
1096 * Interrupt dispatcher
1098 vector_stub irq, IRQ_MODE, 4
1100 .long __irq_usr @ 0 (USR_26 / USR_32)
1101 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1102 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1103 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1104 .long __irq_invalid @ 4
1105 .long __irq_invalid @ 5
1106 .long __irq_invalid @ 6
1107 .long __irq_invalid @ 7
1108 .long __irq_invalid @ 8
1109 .long __irq_invalid @ 9
1110 .long __irq_invalid @ a
1111 .long __irq_invalid @ b
1112 .long __irq_invalid @ c
1113 .long __irq_invalid @ d
1114 .long __irq_invalid @ e
1115 .long __irq_invalid @ f
1118 * Data abort dispatcher
1119 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1121 vector_stub dabt, ABT_MODE, 8
1123 .long __dabt_usr @ 0 (USR_26 / USR_32)
1124 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1125 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1126 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1127 .long __dabt_invalid @ 4
1128 .long __dabt_invalid @ 5
1129 .long __dabt_invalid @ 6
1130 .long __dabt_invalid @ 7
1131 .long __dabt_invalid @ 8
1132 .long __dabt_invalid @ 9
1133 .long __dabt_invalid @ a
1134 .long __dabt_invalid @ b
1135 .long __dabt_invalid @ c
1136 .long __dabt_invalid @ d
1137 .long __dabt_invalid @ e
1138 .long __dabt_invalid @ f
1141 * Prefetch abort dispatcher
1142 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1144 vector_stub pabt, ABT_MODE, 4
1146 .long __pabt_usr @ 0 (USR_26 / USR_32)
1147 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1148 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1149 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1150 .long __pabt_invalid @ 4
1151 .long __pabt_invalid @ 5
1152 .long __pabt_invalid @ 6
1153 .long __pabt_invalid @ 7
1154 .long __pabt_invalid @ 8
1155 .long __pabt_invalid @ 9
1156 .long __pabt_invalid @ a
1157 .long __pabt_invalid @ b
1158 .long __pabt_invalid @ c
1159 .long __pabt_invalid @ d
1160 .long __pabt_invalid @ e
1161 .long __pabt_invalid @ f
1164 * Undef instr entry dispatcher
1165 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1167 vector_stub und, UND_MODE
1169 .long __und_usr @ 0 (USR_26 / USR_32)
1170 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1171 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1172 .long __und_svc @ 3 (SVC_26 / SVC_32)
1173 .long __und_invalid @ 4
1174 .long __und_invalid @ 5
1175 .long __und_invalid @ 6
1176 .long __und_invalid @ 7
1177 .long __und_invalid @ 8
1178 .long __und_invalid @ 9
1179 .long __und_invalid @ a
1180 .long __und_invalid @ b
1181 .long __und_invalid @ c
1182 .long __und_invalid @ d
1183 .long __und_invalid @ e
1184 .long __und_invalid @ f
1188 /*=============================================================================
1190 *-----------------------------------------------------------------------------
1191 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1192 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1193 * Basically to switch modes, we *HAVE* to clobber one register... brain
1194 * damage alert! I don't think that we can execute any code in here in any
1195 * other mode than FIQ... Ok you can switch to another mode, but you can't
1196 * get out of that mode without clobbering one register.
1202 /*=============================================================================
1203 * Address exception handler
1204 *-----------------------------------------------------------------------------
1205 * These aren't too critical.
1206 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1213 * We group all the following data together to optimise
1214 * for CPUs with separate I & D caches.
1224 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1226 .globl __vectors_start
1228 ARM( swi SYS_ERROR0 )
1231 W(b) vector_und + stubs_offset
1232 W(ldr) pc, .LCvswi + stubs_offset
1233 W(b) vector_pabt + stubs_offset
1234 W(b) vector_dabt + stubs_offset
1235 W(b) vector_addrexcptn + stubs_offset
1236 W(b) vector_irq + stubs_offset
1237 W(b) vector_fiq + stubs_offset
1239 .globl __vectors_end
1245 .globl cr_no_alignment