2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
25 #include "entry-header.S"
28 * Interrupt handling. Preserves r7, r8, r9
31 get_irqnr_preamble r5, lr
32 1: get_irqnr_and_base r0, r6, r5, lr
35 @ routine called with r0 = irq number, r1 = struct pt_regs *
44 * this macro assumes that irqstat (r6) and base (r5) are
45 * preserved from get_irqnr_and_base above
47 test_for_ipi r0, r6, r5, lr
52 #ifdef CONFIG_LOCAL_TIMERS
53 test_for_ltirq r0, r6, r5, lr
63 .section .kprobes.text,"ax",%progbits
69 * Invalid mode handlers
71 .macro inv_entry, reason
72 sub sp, sp, #S_FRAME_SIZE
78 inv_entry BAD_PREFETCH
80 ENDPROC(__pabt_invalid)
85 ENDPROC(__dabt_invalid)
90 ENDPROC(__irq_invalid)
93 inv_entry BAD_UNDEFINSTR
96 @ XXX fall through to common_invalid
100 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
106 add r0, sp, #S_PC @ here for interlock avoidance
107 mov r7, #-1 @ "" "" "" ""
108 str r4, [sp] @ save preserved r0
109 stmia r0, {r5 - r7} @ lr_<exception>,
110 @ cpsr_<exception>, "old_r0"
114 ENDPROC(__und_invalid)
120 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
121 #define SPFIX(code...) code
123 #define SPFIX(code...)
126 .macro svc_entry, stack_hole=0
128 UNWIND(.save {r0 - pc} )
129 sub sp, sp, #(S_FRAME_SIZE + \stack_hole)
131 SPFIX( bicne sp, sp, #4 )
135 add r5, sp, #S_SP @ here for interlock avoidance
136 mov r4, #-1 @ "" "" "" ""
137 add r0, sp, #(S_FRAME_SIZE + \stack_hole)
138 SPFIX( addne r0, r0, #4 )
139 str r1, [sp] @ save the "real" r0 copied
140 @ from the exception stack
145 @ We are now ready to fill in the remaining blanks on the stack:
149 @ r2 - lr_<exception>, already fixed up for correct return/restart
150 @ r3 - spsr_<exception>
151 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
155 asm_trace_hardirqs_off
163 @ get ready to re-enable interrupts if appropriate
167 biceq r9, r9, #PSR_I_BIT
170 @ Call the processor-specific abort handler:
172 @ r2 - aborted context pc
173 @ r3 - aborted context cpsr
175 @ The abort handler must return the aborted address in r0, and
176 @ the fault status register in r1. r9 must be preserved.
181 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
183 bl CPU_DABORT_HANDLER
187 @ set desired IRQ state, then call main handler
194 @ IRQs off again before pulling preserved data off the stack
199 @ restore SPSR and restart the instruction
203 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
211 #ifdef CONFIG_PREEMPT
213 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
214 add r7, r8, #1 @ increment it
215 str r7, [tsk, #TI_PREEMPT]
219 #ifdef CONFIG_PREEMPT
220 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
221 ldr r0, [tsk, #TI_FLAGS] @ get flags
222 teq r8, #0 @ if preempt count != 0
223 movne r0, #0 @ force flags to 0
224 tst r0, #_TIF_NEED_RESCHED
227 ldr r0, [sp, #S_PSR] @ irqs are already disabled
229 #ifdef CONFIG_TRACE_IRQFLAGS
231 bleq trace_hardirqs_on
233 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
239 #ifdef CONFIG_PREEMPT
242 1: bl preempt_schedule_irq @ irq en/disable is done inside
243 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
244 tst r0, #_TIF_NEED_RESCHED
245 moveq pc, r8 @ go again
251 #ifdef CONFIG_KPROBES
252 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
253 @ it obviously needs free stack space which then will belong to
261 @ call emulation code, which returns using r9 if it has emulated
262 @ the instruction, or the more conventional lr if we are to treat
263 @ this as a real undefined instruction
271 mov r0, sp @ struct pt_regs *regs
275 @ IRQs off again before pulling preserved data off the stack
280 @ restore SPSR and restart the instruction
282 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
284 ldmia sp, {r0 - pc}^ @ Restore SVC registers
293 @ re-enable interrupts if appropriate
297 biceq r9, r9, #PSR_I_BIT
300 @ set args, then call main handler
302 @ r0 - address of faulting instruction
303 @ r1 - pointer to registers on stack
306 mov r0, r2 @ pass address of aborted instruction.
309 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
311 CPU_PABORT_HANDLER(r0, r2)
313 msr cpsr_c, r9 @ Maybe enable interrupts
315 bl do_PrefetchAbort @ call abort handler
318 @ IRQs off again before pulling preserved data off the stack
323 @ restore SPSR and restart the instruction
327 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
344 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
347 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
348 #error "sizeof(struct pt_regs) must be a multiple of 8"
353 UNWIND(.cantunwind ) @ don't unwind the user space
354 sub sp, sp, #S_FRAME_SIZE
358 add r0, sp, #S_PC @ here for interlock avoidance
359 mov r4, #-1 @ "" "" "" ""
361 str r1, [sp] @ save the "real" r0 copied
362 @ from the exception stack
365 @ We are now ready to fill in the remaining blanks on the stack:
367 @ r2 - lr_<exception>, already fixed up for correct return/restart
368 @ r3 - spsr_<exception>
369 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
371 @ Also, separately save sp_usr and lr_usr
377 @ Enable the alignment trap while in kernel mode
382 @ Clear FP to mark the first stack frame
386 asm_trace_hardirqs_off
389 .macro kuser_cmpxchg_check
390 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
392 #warning "NPTL on non MMU needs fixing"
394 @ Make sure our user space atomic helper is restarted
395 @ if it was interrupted in a critical region. Here we
396 @ perform a quick test inline since it should be false
397 @ 99.9999% of the time. The rest is done out of line.
399 blhs kuser_cmpxchg_fixup
410 @ Call the processor-specific abort handler:
412 @ r2 - aborted context pc
413 @ r3 - aborted context cpsr
415 @ The abort handler must return the aborted address in r0, and
416 @ the fault status register in r1.
421 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
423 bl CPU_DABORT_HANDLER
427 @ IRQs on, then call the main handler
431 adr lr, ret_from_exception
442 #ifdef CONFIG_PREEMPT
443 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
444 add r7, r8, #1 @ increment it
445 str r7, [tsk, #TI_PREEMPT]
449 #ifdef CONFIG_PREEMPT
450 ldr r0, [tsk, #TI_PREEMPT]
451 str r8, [tsk, #TI_PREEMPT]
455 #ifdef CONFIG_TRACE_IRQFLAGS
471 @ fall through to the emulation code, which returns using r9 if
472 @ it has emulated the instruction, or the more conventional lr
473 @ if we are to treat this as a real undefined instruction
477 adr r9, ret_from_exception
478 adr lr, __und_usr_unknown
479 tst r3, #PSR_T_BIT @ Thumb mode?
480 subeq r4, r2, #4 @ ARM instr at LR - 4
481 subne r4, r2, #2 @ Thumb instr at LR - 2
483 #ifdef CONFIG_CPU_ENDIAN_BE8
484 reveq r0, r0 @ little endian instruction
488 #if __LINUX_ARM_ARCH__ >= 7
489 2: ldrht r5, [r4], #2
490 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
491 cmp r0, #0xe800 @ 32bit instruction if xx != 0
492 blo __und_usr_unknown
494 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
495 orr r0, r0, r5, lsl #16
503 @ fallthrough to call_fpe
507 * The out of line fixup for the ldrt above.
509 .section .fixup, "ax"
512 .section __ex_table,"a"
514 #if __LINUX_ARM_ARCH__ >= 7
521 * Check whether the instruction is a co-processor instruction.
522 * If yes, we need to call the relevant co-processor handler.
524 * Note that we don't do a full check here for the co-processor
525 * instructions; all instructions with bit 27 set are well
526 * defined. The only instructions that should fault are the
527 * co-processor instructions. However, we have to watch out
528 * for the ARM6/ARM7 SWI bug.
530 * NEON is a special case that has to be handled here. Not all
531 * NEON instructions are co-processor instructions, so we have
532 * to make a special case of checking for them. Plus, there's
533 * five groups of them, so we have a table of mask/opcode pairs
534 * to check against, and if any match then we branch off into the
537 * Emulators may wish to make use of the following registers:
538 * r0 = instruction opcode.
540 * r9 = normal "successful" return address
541 * r10 = this threads thread_info structure.
542 * lr = unrecognised instruction return address
545 @ Fall-through from Thumb-2 __und_usr
548 adr r6, .LCneon_thumb_opcodes
553 adr r6, .LCneon_arm_opcodes
555 ldr r7, [r6], #4 @ mask value
556 cmp r7, #0 @ end mask?
559 ldr r7, [r6], #4 @ opcode bits matching in mask
560 cmp r8, r7 @ NEON instruction?
564 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
565 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
566 b do_vfp @ let VFP handler handle this
569 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
570 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
571 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
572 and r8, r0, #0x0f000000 @ mask out op-code bits
573 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
576 get_thread_info r10 @ get current thread
577 and r8, r0, #0x00000f00 @ mask out CP number
579 add r6, r10, #TI_USED_CP
580 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
582 @ Test if we need to give access to iWMMXt coprocessors
583 ldr r5, [r10, #TI_FLAGS]
584 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
585 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
586 bcs iwmmxt_task_enable
588 add pc, pc, r8, lsr #6
592 b do_fpe @ CP#1 (FPE)
593 b do_fpe @ CP#2 (FPE)
596 b crunch_task_enable @ CP#4 (MaverickCrunch)
597 b crunch_task_enable @ CP#5 (MaverickCrunch)
598 b crunch_task_enable @ CP#6 (MaverickCrunch)
608 b do_vfp @ CP#10 (VFP)
609 b do_vfp @ CP#11 (VFP)
611 mov pc, lr @ CP#10 (VFP)
612 mov pc, lr @ CP#11 (VFP)
616 mov pc, lr @ CP#14 (Debug)
617 mov pc, lr @ CP#15 (Control)
623 .word 0xfe000000 @ mask
624 .word 0xf2000000 @ opcode
626 .word 0xff100000 @ mask
627 .word 0xf4000000 @ opcode
629 .word 0x00000000 @ mask
630 .word 0x00000000 @ opcode
632 .LCneon_thumb_opcodes:
633 .word 0xef000000 @ mask
634 .word 0xef000000 @ opcode
636 .word 0xff100000 @ mask
637 .word 0xf9000000 @ opcode
639 .word 0x00000000 @ mask
640 .word 0x00000000 @ opcode
646 add r10, r10, #TI_FPSTATE @ r10 = workspace
647 ldr pc, [r4] @ Call FP module USR entry point
650 * The FP module is called with these registers set:
653 * r9 = normal "successful" return address
655 * lr = unrecognised FP instruction return address
668 adr lr, ret_from_exception
670 ENDPROC(__und_usr_unknown)
677 mov r0, r2 @ pass address of aborted instruction.
680 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
682 CPU_PABORT_HANDLER(r0, r2)
684 enable_irq @ Enable interrupts
686 bl do_PrefetchAbort @ call abort handler
690 * This is the return code to user mode for abort handlers
692 ENTRY(ret_from_exception)
700 ENDPROC(ret_from_exception)
703 * Register switch for ARMv3 and ARMv4 processors
704 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
705 * previous and next are guaranteed not to be the same.
710 add ip, r1, #TI_CPU_SAVE
711 ldr r3, [r2, #TI_TP_VALUE]
712 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
714 ldr r6, [r2, #TI_CPU_DOMAIN]
716 #if __LINUX_ARM_ARCH__ >= 6
717 #ifdef CONFIG_CPU_32v6K
720 strex r5, r4, [ip] @ Clear exclusive monitor
723 #if defined(CONFIG_HAS_TLS_REG)
724 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
725 #elif !defined(CONFIG_TLS_REG_EMUL)
727 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
730 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
733 add r4, r2, #TI_CPU_SAVE
734 ldr r0, =thread_notify_head
735 mov r1, #THREAD_NOTIFY_SWITCH
736 bl atomic_notifier_call_chain
738 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
747 * These are segment of kernel provided user code reachable from user space
748 * at a fixed address in kernel memory. This is used to provide user space
749 * with some operations which require kernel help because of unimplemented
750 * native feature and/or instructions in many ARM CPUs. The idea is for
751 * this code to be executed directly in user mode for best efficiency but
752 * which is too intimate with the kernel counter part to be left to user
753 * libraries. In fact this code might even differ from one CPU to another
754 * depending on the available instruction set and restrictions like on
755 * SMP systems. In other words, the kernel reserves the right to change
756 * this code as needed without warning. Only the entry points and their
757 * results are guaranteed to be stable.
759 * Each segment is 32-byte aligned and will be moved to the top of the high
760 * vector page. New segments (if ever needed) must be added in front of
761 * existing ones. This mechanism should be used only for things that are
762 * really small and justified, and not be abused freely.
764 * User space is expected to implement those things inline when optimizing
765 * for a processor that has the necessary native support, but only if such
766 * resulting binaries are already to be incompatible with earlier ARM
767 * processors due to the use of unsupported instructions other than what
768 * is provided here. In other words don't make binaries unable to run on
769 * earlier processors just for the sake of not using these kernel helpers
770 * if your compiled code is not going to use the new instructions for other
775 #ifdef CONFIG_ARM_THUMB
783 .globl __kuser_helper_start
784 __kuser_helper_start:
787 * Reference prototype:
789 * void __kernel_memory_barrier(void)
793 * lr = return address
803 * Definition and user space usage example:
805 * typedef void (__kernel_dmb_t)(void);
806 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
808 * Apply any needed memory barrier to preserve consistency with data modified
809 * manually and __kuser_cmpxchg usage.
811 * This could be used as follows:
813 * #define __kernel_dmb() \
814 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
815 * : : : "r0", "lr","cc" )
818 __kuser_memory_barrier: @ 0xffff0fa0
825 * Reference prototype:
827 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
834 * lr = return address
838 * r0 = returned value (zero or non-zero)
839 * C flag = set if r0 == 0, clear if r0 != 0
845 * Definition and user space usage example:
847 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
848 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
850 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
851 * Return zero if *ptr was changed or non-zero if no exchange happened.
852 * The C flag is also set if *ptr was changed to allow for assembly
853 * optimization in the calling code.
857 * - This routine already includes memory barriers as needed.
859 * For example, a user space atomic_add implementation could look like this:
861 * #define atomic_add(ptr, val) \
862 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
863 * register unsigned int __result asm("r1"); \
865 * "1: @ atomic_add\n\t" \
866 * "ldr r0, [r2]\n\t" \
867 * "mov r3, #0xffff0fff\n\t" \
868 * "add lr, pc, #4\n\t" \
869 * "add r1, r0, %2\n\t" \
870 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
872 * : "=&r" (__result) \
873 * : "r" (__ptr), "rIL" (val) \
874 * : "r0","r3","ip","lr","cc","memory" ); \
878 __kuser_cmpxchg: @ 0xffff0fc0
880 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
883 * Poor you. No fast solution possible...
884 * The kernel itself must perform the operation.
885 * A special ghost syscall is used for that (see traps.c).
888 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
893 #elif __LINUX_ARM_ARCH__ < 6
898 * The only thing that can break atomicity in this cmpxchg
899 * implementation is either an IRQ or a data abort exception
900 * causing another process/thread to be scheduled in the middle
901 * of the critical sequence. To prevent this, code is added to
902 * the IRQ and data abort exception handlers to set the pc back
903 * to the beginning of the critical section if it is found to be
904 * within that critical section (see kuser_cmpxchg_fixup).
906 1: ldr r3, [r2] @ load current val
907 subs r3, r3, r0 @ compare with oldval
908 2: streq r1, [r2] @ store newval if eq
909 rsbs r0, r3, #0 @ set return val and C flag
914 @ Called from kuser_cmpxchg_check macro.
915 @ r2 = address of interrupted insn (must be preserved).
916 @ sp = saved regs. r7 and r8 are clobbered.
917 @ 1b = first critical insn, 2b = last critical insn.
918 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
920 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
922 rsbcss r8, r8, #(2b - 1b)
923 strcs r7, [sp, #S_PC]
928 #warning "NPTL on non MMU needs fixing"
937 mcr p15, 0, r0, c7, c10, 5 @ dmb
945 /* beware -- each __kuser slot must be 8 instructions max */
947 b __kuser_memory_barrier
957 * Reference prototype:
959 * int __kernel_get_tls(void)
963 * lr = return address
973 * Definition and user space usage example:
975 * typedef int (__kernel_get_tls_t)(void);
976 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
978 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
980 * This could be used as follows:
982 * #define __kernel_get_tls() \
983 * ({ register unsigned int __val asm("r0"); \
984 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
985 * : "=r" (__val) : : "lr","cc" ); \
989 __kuser_get_tls: @ 0xffff0fe0
991 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
992 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
994 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
999 .word 0 @ pad up to __kuser_helper_version
1003 * Reference declaration:
1005 * extern unsigned int __kernel_helper_version;
1007 * Definition and user space usage example:
1009 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1011 * User space may read this to determine the curent number of helpers
1015 __kuser_helper_version: @ 0xffff0ffc
1016 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1018 .globl __kuser_helper_end
1025 * This code is copied to 0xffff0200 so we can use branches in the
1026 * vectors, rather than ldr's. Note that this code must not
1027 * exceed 0x300 bytes.
1029 * Common stub entry macro:
1030 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1032 * SP points to a minimal amount of processor-private memory, the address
1033 * of which is copied into r0 for the mode specific abort handler.
1035 .macro vector_stub, name, mode, correction=0
1040 sub lr, lr, #\correction
1044 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1047 stmia sp, {r0, lr} @ save r0, lr
1049 str lr, [sp, #8] @ save spsr
1052 @ Prepare for SVC32 mode. IRQs remain disabled.
1055 eor r0, r0, #(\mode ^ SVC_MODE)
1059 @ the branch table must immediately follow this code
1063 ldr lr, [pc, lr, lsl #2]
1064 movs pc, lr @ branch to handler in SVC mode
1065 ENDPROC(vector_\name)
1068 .globl __stubs_start
1071 * Interrupt dispatcher
1073 vector_stub irq, IRQ_MODE, 4
1075 .long __irq_usr @ 0 (USR_26 / USR_32)
1076 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1077 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1078 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1079 .long __irq_invalid @ 4
1080 .long __irq_invalid @ 5
1081 .long __irq_invalid @ 6
1082 .long __irq_invalid @ 7
1083 .long __irq_invalid @ 8
1084 .long __irq_invalid @ 9
1085 .long __irq_invalid @ a
1086 .long __irq_invalid @ b
1087 .long __irq_invalid @ c
1088 .long __irq_invalid @ d
1089 .long __irq_invalid @ e
1090 .long __irq_invalid @ f
1093 * Data abort dispatcher
1094 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1096 vector_stub dabt, ABT_MODE, 8
1098 .long __dabt_usr @ 0 (USR_26 / USR_32)
1099 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1100 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1101 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1102 .long __dabt_invalid @ 4
1103 .long __dabt_invalid @ 5
1104 .long __dabt_invalid @ 6
1105 .long __dabt_invalid @ 7
1106 .long __dabt_invalid @ 8
1107 .long __dabt_invalid @ 9
1108 .long __dabt_invalid @ a
1109 .long __dabt_invalid @ b
1110 .long __dabt_invalid @ c
1111 .long __dabt_invalid @ d
1112 .long __dabt_invalid @ e
1113 .long __dabt_invalid @ f
1116 * Prefetch abort dispatcher
1117 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1119 vector_stub pabt, ABT_MODE, 4
1121 .long __pabt_usr @ 0 (USR_26 / USR_32)
1122 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1123 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1124 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1125 .long __pabt_invalid @ 4
1126 .long __pabt_invalid @ 5
1127 .long __pabt_invalid @ 6
1128 .long __pabt_invalid @ 7
1129 .long __pabt_invalid @ 8
1130 .long __pabt_invalid @ 9
1131 .long __pabt_invalid @ a
1132 .long __pabt_invalid @ b
1133 .long __pabt_invalid @ c
1134 .long __pabt_invalid @ d
1135 .long __pabt_invalid @ e
1136 .long __pabt_invalid @ f
1139 * Undef instr entry dispatcher
1140 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1142 vector_stub und, UND_MODE
1144 .long __und_usr @ 0 (USR_26 / USR_32)
1145 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1146 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1147 .long __und_svc @ 3 (SVC_26 / SVC_32)
1148 .long __und_invalid @ 4
1149 .long __und_invalid @ 5
1150 .long __und_invalid @ 6
1151 .long __und_invalid @ 7
1152 .long __und_invalid @ 8
1153 .long __und_invalid @ 9
1154 .long __und_invalid @ a
1155 .long __und_invalid @ b
1156 .long __und_invalid @ c
1157 .long __und_invalid @ d
1158 .long __und_invalid @ e
1159 .long __und_invalid @ f
1163 /*=============================================================================
1165 *-----------------------------------------------------------------------------
1166 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1167 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1168 * Basically to switch modes, we *HAVE* to clobber one register... brain
1169 * damage alert! I don't think that we can execute any code in here in any
1170 * other mode than FIQ... Ok you can switch to another mode, but you can't
1171 * get out of that mode without clobbering one register.
1177 /*=============================================================================
1178 * Address exception handler
1179 *-----------------------------------------------------------------------------
1180 * These aren't too critical.
1181 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1188 * We group all the following data together to optimise
1189 * for CPUs with separate I & D caches.
1199 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1201 .globl __vectors_start
1204 b vector_und + stubs_offset
1205 ldr pc, .LCvswi + stubs_offset
1206 b vector_pabt + stubs_offset
1207 b vector_dabt + stubs_offset
1208 b vector_addrexcptn + stubs_offset
1209 b vector_irq + stubs_offset
1210 b vector_fiq + stubs_offset
1212 .globl __vectors_end
1218 .globl cr_no_alignment