2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/assembler.h>
19 #include <asm/memory.h>
20 #include <asm/glue-df.h>
21 #include <asm/glue-pf.h>
22 #include <asm/vfpmacros.h>
23 #ifndef CONFIG_MULTI_IRQ_HANDLER
24 #include <mach/entry-macro.S>
26 #include <asm/thread_notify.h>
27 #include <asm/unwind.h>
28 #include <asm/unistd.h>
30 #include <asm/system_info.h>
32 #include "entry-header.S"
33 #include <asm/entry-macro-multi.S>
39 #ifdef CONFIG_MULTI_IRQ_HANDLER
40 ldr r1, =handle_arch_irq
45 arch_irq_handler_default
51 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
55 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
64 @ Call the processor-specific abort handler:
67 @ r4 - aborted context pc
68 @ r5 - aborted context psr
70 @ The abort handler must return the aborted address in r0, and
71 @ the fault status register in r1. r9 must be preserved.
76 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
83 .section .kprobes.text,"ax",%progbits
89 * Invalid mode handlers
91 .macro inv_entry, reason
92 sub sp, sp, #S_FRAME_SIZE
93 ARM( stmib sp, {r1 - lr} )
94 THUMB( stmia sp, {r0 - r12} )
95 THUMB( str sp, [sp, #S_SP] )
96 THUMB( str lr, [sp, #S_LR] )
101 inv_entry BAD_PREFETCH
103 ENDPROC(__pabt_invalid)
108 ENDPROC(__dabt_invalid)
113 ENDPROC(__irq_invalid)
116 inv_entry BAD_UNDEFINSTR
119 @ XXX fall through to common_invalid
123 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
129 add r0, sp, #S_PC @ here for interlock avoidance
130 mov r7, #-1 @ "" "" "" ""
131 str r4, [sp] @ save preserved r0
132 stmia r0, {r5 - r7} @ lr_<exception>,
133 @ cpsr_<exception>, "old_r0"
137 ENDPROC(__und_invalid)
143 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
144 #define SPFIX(code...) code
146 #define SPFIX(code...)
149 .macro svc_entry, stack_hole=0
151 UNWIND(.save {r0 - pc} )
152 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
153 #ifdef CONFIG_THUMB2_KERNEL
154 SPFIX( str r0, [sp] ) @ temporarily saved
156 SPFIX( tst r0, #4 ) @ test original stack alignment
157 SPFIX( ldr r0, [sp] ) @ restored
161 SPFIX( subeq sp, sp, #4 )
165 add r7, sp, #S_SP - 4 @ here for interlock avoidance
166 mov r6, #-1 @ "" "" "" ""
167 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
168 SPFIX( addeq r2, r2, #4 )
169 str r3, [sp, #-4]! @ save the "real" r0 copied
170 @ from the exception stack
175 @ We are now ready to fill in the remaining blanks on the stack:
179 @ r4 - lr_<exception>, already fixed up for correct return/restart
180 @ r5 - spsr_<exception>
181 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
185 #ifdef CONFIG_TRACE_IRQFLAGS
186 bl trace_hardirqs_off
195 svc_exit r5 @ return from exception
204 #ifdef CONFIG_PREEMPT
206 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
207 ldr r0, [tsk, #TI_FLAGS] @ get flags
208 teq r8, #0 @ if preempt count != 0
209 movne r0, #0 @ force flags to 0
210 tst r0, #_TIF_NEED_RESCHED
214 svc_exit r5, irq = 1 @ return from exception
220 #ifdef CONFIG_PREEMPT
223 1: bl preempt_schedule_irq @ irq en/disable is done inside
224 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
225 tst r0, #_TIF_NEED_RESCHED
226 moveq pc, r8 @ go again
231 @ Correct the PC such that it is pointing at the instruction
232 @ which caused the fault. If the faulting instruction was ARM
233 @ the PC will be pointing at the next instruction, and have to
234 @ subtract 4. Otherwise, it is Thumb, and the PC will be
235 @ pointing at the second half of the Thumb instruction. We
236 @ have to subtract 2.
245 #ifdef CONFIG_KPROBES
246 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
247 @ it obviously needs free stack space which then will belong to
254 @ call emulation code, which returns using r9 if it has emulated
255 @ the instruction, or the more conventional lr if we are to treat
256 @ this as a real undefined instruction
260 #ifndef CONFIG_THUMB2_KERNEL
264 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
265 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
267 ldrh r9, [r4] @ bottom 16 bits
270 orr r0, r9, r0, lsl #16
272 adr r9, BSYM(__und_svc_finish)
276 mov r1, #4 @ PC correction to apply
278 mov r0, sp @ struct pt_regs *regs
282 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
283 svc_exit r5 @ return from exception
292 svc_exit r5 @ return from exception
309 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
312 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
313 #error "sizeof(struct pt_regs) must be a multiple of 8"
318 UNWIND(.cantunwind ) @ don't unwind the user space
319 sub sp, sp, #S_FRAME_SIZE
320 ARM( stmib sp, {r1 - r12} )
321 THUMB( stmia sp, {r0 - r12} )
324 add r0, sp, #S_PC @ here for interlock avoidance
325 mov r6, #-1 @ "" "" "" ""
327 str r3, [sp] @ save the "real" r0 copied
328 @ from the exception stack
331 @ We are now ready to fill in the remaining blanks on the stack:
333 @ r4 - lr_<exception>, already fixed up for correct return/restart
334 @ r5 - spsr_<exception>
335 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
337 @ Also, separately save sp_usr and lr_usr
340 ARM( stmdb r0, {sp, lr}^ )
341 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
344 @ Enable the alignment trap while in kernel mode
349 @ Clear FP to mark the first stack frame
353 #ifdef CONFIG_IRQSOFF_TRACER
354 bl trace_hardirqs_off
356 ct_user_exit save = 0
359 .macro kuser_cmpxchg_check
360 #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
362 #warning "NPTL on non MMU needs fixing"
364 @ Make sure our user space atomic helper is restarted
365 @ if it was interrupted in a critical region. Here we
366 @ perform a quick test inline since it should be false
367 @ 99.9999% of the time. The rest is done out of line.
369 blhs kuser_cmpxchg64_fixup
391 b ret_to_user_from_irq
404 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
405 @ faulting instruction depending on Thumb mode.
406 @ r3 = regs->ARM_cpsr
408 @ The emulation code returns using r9 if it has emulated the
409 @ instruction, or the more conventional lr if we are to treat
410 @ this as a real undefined instruction
412 adr r9, BSYM(ret_from_exception)
414 tst r3, #PSR_T_BIT @ Thumb mode?
416 sub r4, r2, #4 @ ARM instr at LR - 4
418 #ifdef CONFIG_CPU_ENDIAN_BE8
419 rev r0, r0 @ little endian instruction
421 @ r0 = 32-bit ARM instruction which caused the exception
422 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
423 @ r4 = PC value for the faulting instruction
424 @ lr = 32-bit undefined instruction function
425 adr lr, BSYM(__und_usr_fault_32)
430 sub r4, r2, #2 @ First half of thumb instr at LR - 2
431 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
433 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
434 * can never be supported in a single kernel, this code is not applicable at
435 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
436 * made about .arch directives.
438 #if __LINUX_ARM_ARCH__ < 7
439 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
440 #define NEED_CPU_ARCHITECTURE
441 ldr r5, .LCcpu_architecture
443 cmp r5, #CPU_ARCH_ARMv7
444 blo __und_usr_fault_16 @ 16bit undefined instruction
446 * The following code won't get run unless the running CPU really is v7, so
447 * coding round the lack of ldrht on older arches is pointless. Temporarily
448 * override the assembler target arch with the minimum required instead:
453 cmp r5, #0xe800 @ 32bit instruction if xx != 0
454 blo __und_usr_fault_16 @ 16bit undefined instruction
456 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
457 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
458 orr r0, r0, r5, lsl #16
459 adr lr, BSYM(__und_usr_fault_32)
460 @ r0 = the two 16-bit Thumb instructions which caused the exception
461 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
462 @ r4 = PC value for the first 16-bit Thumb instruction
463 @ lr = 32bit undefined instruction function
465 #if __LINUX_ARM_ARCH__ < 7
466 /* If the target arch was overridden, change it back: */
467 #ifdef CONFIG_CPU_32v6K
472 #endif /* __LINUX_ARM_ARCH__ < 7 */
473 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
480 * The out of line fixup for the ldrt instructions above.
482 .pushsection .fixup, "ax"
486 .pushsection __ex_table,"a"
488 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
495 * Check whether the instruction is a co-processor instruction.
496 * If yes, we need to call the relevant co-processor handler.
498 * Note that we don't do a full check here for the co-processor
499 * instructions; all instructions with bit 27 set are well
500 * defined. The only instructions that should fault are the
501 * co-processor instructions. However, we have to watch out
502 * for the ARM6/ARM7 SWI bug.
504 * NEON is a special case that has to be handled here. Not all
505 * NEON instructions are co-processor instructions, so we have
506 * to make a special case of checking for them. Plus, there's
507 * five groups of them, so we have a table of mask/opcode pairs
508 * to check against, and if any match then we branch off into the
511 * Emulators may wish to make use of the following registers:
512 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
513 * r2 = PC value to resume execution after successful emulation
514 * r9 = normal "successful" return address
515 * r10 = this threads thread_info structure
516 * lr = unrecognised instruction return address
517 * IRQs disabled, FIQs enabled.
520 @ Fall-through from Thumb-2 __und_usr
523 get_thread_info r10 @ get current thread
524 adr r6, .LCneon_thumb_opcodes
528 get_thread_info r10 @ get current thread
530 adr r6, .LCneon_arm_opcodes
531 2: ldr r5, [r6], #4 @ mask value
532 ldr r7, [r6], #4 @ opcode bits matching in mask
533 cmp r5, #0 @ end mask?
536 cmp r8, r7 @ NEON instruction?
539 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
540 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
541 b do_vfp @ let VFP handler handle this
544 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
545 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
547 and r8, r0, #0x00000f00 @ mask out CP number
548 THUMB( lsr r8, r8, #8 )
550 add r6, r10, #TI_USED_CP
551 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
552 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
554 @ Test if we need to give access to iWMMXt coprocessors
555 ldr r5, [r10, #TI_FLAGS]
556 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
557 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
558 bcs iwmmxt_task_enable
560 ARM( add pc, pc, r8, lsr #6 )
561 THUMB( lsl r8, r8, #2 )
566 W(b) do_fpe @ CP#1 (FPE)
567 W(b) do_fpe @ CP#2 (FPE)
570 b crunch_task_enable @ CP#4 (MaverickCrunch)
571 b crunch_task_enable @ CP#5 (MaverickCrunch)
572 b crunch_task_enable @ CP#6 (MaverickCrunch)
582 W(b) do_vfp @ CP#10 (VFP)
583 W(b) do_vfp @ CP#11 (VFP)
585 movw_pc lr @ CP#10 (VFP)
586 movw_pc lr @ CP#11 (VFP)
590 movw_pc lr @ CP#14 (Debug)
591 movw_pc lr @ CP#15 (Control)
593 #ifdef NEED_CPU_ARCHITECTURE
596 .word __cpu_architecture
603 .word 0xfe000000 @ mask
604 .word 0xf2000000 @ opcode
606 .word 0xff100000 @ mask
607 .word 0xf4000000 @ opcode
609 .word 0x00000000 @ mask
610 .word 0x00000000 @ opcode
612 .LCneon_thumb_opcodes:
613 .word 0xef000000 @ mask
614 .word 0xef000000 @ opcode
616 .word 0xff100000 @ mask
617 .word 0xf9000000 @ opcode
619 .word 0x00000000 @ mask
620 .word 0x00000000 @ opcode
626 add r10, r10, #TI_FPSTATE @ r10 = workspace
627 ldr pc, [r4] @ Call FP module USR entry point
630 * The FP module is called with these registers set:
633 * r9 = normal "successful" return address
635 * lr = unrecognised FP instruction return address
654 adr lr, BSYM(ret_from_exception)
656 ENDPROC(__und_usr_fault_32)
657 ENDPROC(__und_usr_fault_16)
667 * This is the return code to user mode for abort handlers
669 ENTRY(ret_from_exception)
677 ENDPROC(ret_from_exception)
680 * Register switch for ARMv3 and ARMv4 processors
681 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
682 * previous and next are guaranteed not to be the same.
687 add ip, r1, #TI_CPU_SAVE
688 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
689 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
690 THUMB( str sp, [ip], #4 )
691 THUMB( str lr, [ip], #4 )
692 ldr r4, [r2, #TI_TP_VALUE]
693 ldr r5, [r2, #TI_TP_VALUE + 4]
694 #ifdef CONFIG_CPU_USE_DOMAINS
695 ldr r6, [r2, #TI_CPU_DOMAIN]
697 switch_tls r1, r4, r5, r3, r7
698 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
699 ldr r7, [r2, #TI_TASK]
700 ldr r8, =__stack_chk_guard
701 ldr r7, [r7, #TSK_STACK_CANARY]
703 #ifdef CONFIG_CPU_USE_DOMAINS
704 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
707 add r4, r2, #TI_CPU_SAVE
708 ldr r0, =thread_notify_head
709 mov r1, #THREAD_NOTIFY_SWITCH
710 bl atomic_notifier_call_chain
711 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
716 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
717 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
718 THUMB( ldr sp, [ip], #4 )
719 THUMB( ldr pc, [ip] )
728 * Each segment is 32-byte aligned and will be moved to the top of the high
729 * vector page. New segments (if ever needed) must be added in front of
730 * existing ones. This mechanism should be used only for things that are
731 * really small and justified, and not be abused freely.
733 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
738 #ifdef CONFIG_ARM_THUMB
745 .macro kuser_pad, sym, size
747 .rept 4 - (. - \sym) & 3
751 .rept (\size - (. - \sym)) / 4
757 .globl __kuser_helper_start
758 __kuser_helper_start:
761 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
762 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
765 __kuser_cmpxchg64: @ 0xffff0f60
767 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
770 * Poor you. No fast solution possible...
771 * The kernel itself must perform the operation.
772 * A special ghost syscall is used for that (see traps.c).
775 ldr r7, 1f @ it's 20 bits
776 swi __ARM_NR_cmpxchg64
778 1: .word __ARM_NR_cmpxchg64
780 #elif defined(CONFIG_CPU_32v6K)
782 stmfd sp!, {r4, r5, r6, r7}
783 ldrd r4, r5, [r0] @ load old val
784 ldrd r6, r7, [r1] @ load new val
786 1: ldrexd r0, r1, [r2] @ load current val
787 eors r3, r0, r4 @ compare with oldval (1)
788 eoreqs r3, r1, r5 @ compare with oldval (2)
789 strexdeq r3, r6, r7, [r2] @ store newval if eq
790 teqeq r3, #1 @ success?
791 beq 1b @ if no then retry
793 rsbs r0, r3, #0 @ set returned val and C flag
794 ldmfd sp!, {r4, r5, r6, r7}
797 #elif !defined(CONFIG_SMP)
802 * The only thing that can break atomicity in this cmpxchg64
803 * implementation is either an IRQ or a data abort exception
804 * causing another process/thread to be scheduled in the middle of
805 * the critical sequence. The same strategy as for cmpxchg is used.
807 stmfd sp!, {r4, r5, r6, lr}
808 ldmia r0, {r4, r5} @ load old val
809 ldmia r1, {r6, lr} @ load new val
810 1: ldmia r2, {r0, r1} @ load current val
811 eors r3, r0, r4 @ compare with oldval (1)
812 eoreqs r3, r1, r5 @ compare with oldval (2)
813 2: stmeqia r2, {r6, lr} @ store newval if eq
814 rsbs r0, r3, #0 @ set return val and C flag
815 ldmfd sp!, {r4, r5, r6, pc}
818 kuser_cmpxchg64_fixup:
819 @ Called from kuser_cmpxchg_fixup.
820 @ r4 = address of interrupted insn (must be preserved).
821 @ sp = saved regs. r7 and r8 are clobbered.
822 @ 1b = first critical insn, 2b = last critical insn.
823 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
825 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
827 rsbcss r8, r8, #(2b - 1b)
828 strcs r7, [sp, #S_PC]
829 #if __LINUX_ARM_ARCH__ < 6
830 bcc kuser_cmpxchg32_fixup
836 #warning "NPTL on non MMU needs fixing"
843 #error "incoherent kernel configuration"
846 kuser_pad __kuser_cmpxchg64, 64
848 __kuser_memory_barrier: @ 0xffff0fa0
852 kuser_pad __kuser_memory_barrier, 32
854 __kuser_cmpxchg: @ 0xffff0fc0
856 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
859 * Poor you. No fast solution possible...
860 * The kernel itself must perform the operation.
861 * A special ghost syscall is used for that (see traps.c).
864 ldr r7, 1f @ it's 20 bits
867 1: .word __ARM_NR_cmpxchg
869 #elif __LINUX_ARM_ARCH__ < 6
874 * The only thing that can break atomicity in this cmpxchg
875 * implementation is either an IRQ or a data abort exception
876 * causing another process/thread to be scheduled in the middle
877 * of the critical sequence. To prevent this, code is added to
878 * the IRQ and data abort exception handlers to set the pc back
879 * to the beginning of the critical section if it is found to be
880 * within that critical section (see kuser_cmpxchg_fixup).
882 1: ldr r3, [r2] @ load current val
883 subs r3, r3, r0 @ compare with oldval
884 2: streq r1, [r2] @ store newval if eq
885 rsbs r0, r3, #0 @ set return val and C flag
889 kuser_cmpxchg32_fixup:
890 @ Called from kuser_cmpxchg_check macro.
891 @ r4 = address of interrupted insn (must be preserved).
892 @ sp = saved regs. r7 and r8 are clobbered.
893 @ 1b = first critical insn, 2b = last critical insn.
894 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
896 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
898 rsbcss r8, r8, #(2b - 1b)
899 strcs r7, [sp, #S_PC]
904 #warning "NPTL on non MMU needs fixing"
919 /* beware -- each __kuser slot must be 8 instructions max */
920 ALT_SMP(b __kuser_memory_barrier)
925 kuser_pad __kuser_cmpxchg, 32
927 __kuser_get_tls: @ 0xffff0fe0
928 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
930 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
931 kuser_pad __kuser_get_tls, 16
933 .word 0 @ 0xffff0ff0 software TLS value, then
934 .endr @ pad up to __kuser_helper_version
936 __kuser_helper_version: @ 0xffff0ffc
937 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
939 .globl __kuser_helper_end
947 * This code is copied to 0xffff1000 so we can use branches in the
948 * vectors, rather than ldr's. Note that this code must not exceed
951 * Common stub entry macro:
952 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
954 * SP points to a minimal amount of processor-private memory, the address
955 * of which is copied into r0 for the mode specific abort handler.
957 .macro vector_stub, name, mode, correction=0
962 sub lr, lr, #\correction
966 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
969 stmia sp, {r0, lr} @ save r0, lr
971 str lr, [sp, #8] @ save spsr
974 @ Prepare for SVC32 mode. IRQs remain disabled.
977 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
981 @ the branch table must immediately follow this code
985 THUMB( ldr lr, [r0, lr, lsl #2] )
987 ARM( ldr lr, [pc, lr, lsl #2] )
988 movs pc, lr @ branch to handler in SVC mode
989 ENDPROC(vector_\name)
992 @ handler addresses follow this label
996 .section .stubs, "ax", %progbits
998 @ This must be the first word
1002 ARM( swi SYS_ERROR0 )
1008 * Interrupt dispatcher
1010 vector_stub irq, IRQ_MODE, 4
1012 .long __irq_usr @ 0 (USR_26 / USR_32)
1013 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1014 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1015 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1016 .long __irq_invalid @ 4
1017 .long __irq_invalid @ 5
1018 .long __irq_invalid @ 6
1019 .long __irq_invalid @ 7
1020 .long __irq_invalid @ 8
1021 .long __irq_invalid @ 9
1022 .long __irq_invalid @ a
1023 .long __irq_invalid @ b
1024 .long __irq_invalid @ c
1025 .long __irq_invalid @ d
1026 .long __irq_invalid @ e
1027 .long __irq_invalid @ f
1030 * Data abort dispatcher
1031 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1033 vector_stub dabt, ABT_MODE, 8
1035 .long __dabt_usr @ 0 (USR_26 / USR_32)
1036 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1037 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1038 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1039 .long __dabt_invalid @ 4
1040 .long __dabt_invalid @ 5
1041 .long __dabt_invalid @ 6
1042 .long __dabt_invalid @ 7
1043 .long __dabt_invalid @ 8
1044 .long __dabt_invalid @ 9
1045 .long __dabt_invalid @ a
1046 .long __dabt_invalid @ b
1047 .long __dabt_invalid @ c
1048 .long __dabt_invalid @ d
1049 .long __dabt_invalid @ e
1050 .long __dabt_invalid @ f
1053 * Prefetch abort dispatcher
1054 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1056 vector_stub pabt, ABT_MODE, 4
1058 .long __pabt_usr @ 0 (USR_26 / USR_32)
1059 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1060 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1061 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1062 .long __pabt_invalid @ 4
1063 .long __pabt_invalid @ 5
1064 .long __pabt_invalid @ 6
1065 .long __pabt_invalid @ 7
1066 .long __pabt_invalid @ 8
1067 .long __pabt_invalid @ 9
1068 .long __pabt_invalid @ a
1069 .long __pabt_invalid @ b
1070 .long __pabt_invalid @ c
1071 .long __pabt_invalid @ d
1072 .long __pabt_invalid @ e
1073 .long __pabt_invalid @ f
1076 * Undef instr entry dispatcher
1077 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1079 vector_stub und, UND_MODE
1081 .long __und_usr @ 0 (USR_26 / USR_32)
1082 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1083 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1084 .long __und_svc @ 3 (SVC_26 / SVC_32)
1085 .long __und_invalid @ 4
1086 .long __und_invalid @ 5
1087 .long __und_invalid @ 6
1088 .long __und_invalid @ 7
1089 .long __und_invalid @ 8
1090 .long __und_invalid @ 9
1091 .long __und_invalid @ a
1092 .long __und_invalid @ b
1093 .long __und_invalid @ c
1094 .long __und_invalid @ d
1095 .long __und_invalid @ e
1096 .long __und_invalid @ f
1100 /*=============================================================================
1101 * Address exception handler
1102 *-----------------------------------------------------------------------------
1103 * These aren't too critical.
1104 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1110 /*=============================================================================
1112 *-----------------------------------------------------------------------------
1113 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1114 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1115 * Basically to switch modes, we *HAVE* to clobber one register... brain
1116 * damage alert! I don't think that we can execute any code in here in any
1117 * other mode than FIQ... Ok you can switch to another mode, but you can't
1118 * get out of that mode without clobbering one register.
1123 .section .vectors, "ax", %progbits
1127 W(ldr) pc, __vectors_start + 0x1000
1130 W(b) vector_addrexcptn
1137 .globl cr_no_alignment
1143 #ifdef CONFIG_MULTI_IRQ_HANDLER
1144 .globl handle_arch_irq