2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24 #include <asm/unistd.h>
27 #include "entry-header.S"
30 * Interrupt handling. Preserves r7, r8, r9
33 get_irqnr_preamble r5, lr
34 1: get_irqnr_and_base r0, r6, r5, lr
37 @ routine called with r0 = irq number, r1 = struct pt_regs *
46 * this macro assumes that irqstat (r6) and base (r5) are
47 * preserved from get_irqnr_and_base above
49 ALT_SMP(test_for_ipi r0, r6, r5, lr)
55 #ifdef CONFIG_LOCAL_TIMERS
56 test_for_ltirq r0, r6, r5, lr
67 .section .kprobes.text,"ax",%progbits
73 * Invalid mode handlers
75 .macro inv_entry, reason
76 sub sp, sp, #S_FRAME_SIZE
77 ARM( stmib sp, {r1 - lr} )
78 THUMB( stmia sp, {r0 - r12} )
79 THUMB( str sp, [sp, #S_SP] )
80 THUMB( str lr, [sp, #S_LR] )
85 inv_entry BAD_PREFETCH
87 ENDPROC(__pabt_invalid)
92 ENDPROC(__dabt_invalid)
97 ENDPROC(__irq_invalid)
100 inv_entry BAD_UNDEFINSTR
103 @ XXX fall through to common_invalid
107 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
113 add r0, sp, #S_PC @ here for interlock avoidance
114 mov r7, #-1 @ "" "" "" ""
115 str r4, [sp] @ save preserved r0
116 stmia r0, {r5 - r7} @ lr_<exception>,
117 @ cpsr_<exception>, "old_r0"
121 ENDPROC(__und_invalid)
127 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
128 #define SPFIX(code...) code
130 #define SPFIX(code...)
133 .macro svc_entry, stack_hole=0
135 UNWIND(.save {r0 - pc} )
136 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
137 #ifdef CONFIG_THUMB2_KERNEL
138 SPFIX( str r0, [sp] ) @ temporarily saved
140 SPFIX( tst r0, #4 ) @ test original stack alignment
141 SPFIX( ldr r0, [sp] ) @ restored
145 SPFIX( subeq sp, sp, #4 )
149 add r5, sp, #S_SP - 4 @ here for interlock avoidance
150 mov r4, #-1 @ "" "" "" ""
151 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
152 SPFIX( addeq r0, r0, #4 )
153 str r1, [sp, #-4]! @ save the "real" r0 copied
154 @ from the exception stack
159 @ We are now ready to fill in the remaining blanks on the stack:
163 @ r2 - lr_<exception>, already fixed up for correct return/restart
164 @ r3 - spsr_<exception>
165 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
175 @ get ready to re-enable interrupts if appropriate
179 biceq r9, r9, #PSR_I_BIT
182 @ Call the processor-specific abort handler:
184 @ r2 - aborted context pc
185 @ r3 - aborted context cpsr
187 @ The abort handler must return the aborted address in r0, and
188 @ the fault status register in r1. r9 must be preserved.
193 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
195 bl CPU_DABORT_HANDLER
199 @ set desired IRQ state, then call main handler
207 @ IRQs off again before pulling preserved data off the stack
212 @ restore SPSR and restart the instruction
215 svc_exit r2 @ return from exception
223 #ifdef CONFIG_TRACE_IRQFLAGS
224 bl trace_hardirqs_off
226 #ifdef CONFIG_PREEMPT
228 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
229 add r7, r8, #1 @ increment it
230 str r7, [tsk, #TI_PREEMPT]
234 #ifdef CONFIG_PREEMPT
235 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
236 ldr r0, [tsk, #TI_FLAGS] @ get flags
237 teq r8, #0 @ if preempt count != 0
238 movne r0, #0 @ force flags to 0
239 tst r0, #_TIF_NEED_RESCHED
242 ldr r4, [sp, #S_PSR] @ irqs are already disabled
243 #ifdef CONFIG_TRACE_IRQFLAGS
245 bleq trace_hardirqs_on
247 svc_exit r4 @ return from exception
253 #ifdef CONFIG_PREEMPT
256 1: bl preempt_schedule_irq @ irq en/disable is done inside
257 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
258 tst r0, #_TIF_NEED_RESCHED
259 moveq pc, r8 @ go again
265 #ifdef CONFIG_KPROBES
266 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
267 @ it obviously needs free stack space which then will belong to
275 @ call emulation code, which returns using r9 if it has emulated
276 @ the instruction, or the more conventional lr if we are to treat
277 @ this as a real undefined instruction
281 #ifndef CONFIG_THUMB2_KERNEL
284 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
286 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
287 ldrhhs r9, [r2] @ bottom 16 bits
288 orrhs r0, r9, r0, lsl #16
293 mov r0, sp @ struct pt_regs *regs
297 @ IRQs off again before pulling preserved data off the stack
299 1: disable_irq_notrace
302 @ restore SPSR and restart the instruction
304 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
305 svc_exit r2 @ return from exception
314 @ re-enable interrupts if appropriate
318 biceq r9, r9, #PSR_I_BIT
320 mov r0, r2 @ pass address of aborted instruction.
324 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
326 bl CPU_PABORT_HANDLER
329 msr cpsr_c, r9 @ Maybe enable interrupts
331 bl do_PrefetchAbort @ call abort handler
334 @ IRQs off again before pulling preserved data off the stack
339 @ restore SPSR and restart the instruction
342 svc_exit r2 @ return from exception
359 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
362 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
363 #error "sizeof(struct pt_regs) must be a multiple of 8"
368 UNWIND(.cantunwind ) @ don't unwind the user space
369 sub sp, sp, #S_FRAME_SIZE
370 ARM( stmib sp, {r1 - r12} )
371 THUMB( stmia sp, {r0 - r12} )
374 add r0, sp, #S_PC @ here for interlock avoidance
375 mov r4, #-1 @ "" "" "" ""
377 str r1, [sp] @ save the "real" r0 copied
378 @ from the exception stack
381 @ We are now ready to fill in the remaining blanks on the stack:
383 @ r2 - lr_<exception>, already fixed up for correct return/restart
384 @ r3 - spsr_<exception>
385 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
387 @ Also, separately save sp_usr and lr_usr
390 ARM( stmdb r0, {sp, lr}^ )
391 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
394 @ Enable the alignment trap while in kernel mode
399 @ Clear FP to mark the first stack frame
404 .macro kuser_cmpxchg_check
405 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
407 #warning "NPTL on non MMU needs fixing"
409 @ Make sure our user space atomic helper is restarted
410 @ if it was interrupted in a critical region. Here we
411 @ perform a quick test inline since it should be false
412 @ 99.9999% of the time. The rest is done out of line.
414 blhs kuser_cmpxchg_fixup
425 @ Call the processor-specific abort handler:
427 @ r2 - aborted context pc
428 @ r3 - aborted context cpsr
430 @ The abort handler must return the aborted address in r0, and
431 @ the fault status register in r1.
436 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
438 bl CPU_DABORT_HANDLER
442 @ IRQs on, then call the main handler
447 adr lr, BSYM(ret_from_exception)
458 #ifdef CONFIG_PREEMPT
459 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
460 add r7, r8, #1 @ increment it
461 str r7, [tsk, #TI_PREEMPT]
465 #ifdef CONFIG_PREEMPT
466 ldr r0, [tsk, #TI_PREEMPT]
467 str r8, [tsk, #TI_PREEMPT]
469 ARM( strne r0, [r0, -r0] )
470 THUMB( movne r0, #0 )
471 THUMB( strne r0, [r0] )
486 @ fall through to the emulation code, which returns using r9 if
487 @ it has emulated the instruction, or the more conventional lr
488 @ if we are to treat this as a real undefined instruction
492 adr r9, BSYM(ret_from_exception)
493 adr lr, BSYM(__und_usr_unknown)
494 tst r3, #PSR_T_BIT @ Thumb mode?
495 itet eq @ explicit IT needed for the 1f label
496 subeq r4, r2, #4 @ ARM instr at LR - 4
497 subne r4, r2, #2 @ Thumb instr at LR - 2
499 #ifdef CONFIG_CPU_ENDIAN_BE8
500 reveq r0, r0 @ little endian instruction
504 #if __LINUX_ARM_ARCH__ >= 7
506 ARM( ldrht r5, [r4], #2 )
507 THUMB( ldrht r5, [r4] )
508 THUMB( add r4, r4, #2 )
509 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
510 cmp r0, #0xe800 @ 32bit instruction if xx != 0
511 blo __und_usr_unknown
513 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
514 orr r0, r0, r5, lsl #16
522 @ fallthrough to call_fpe
526 * The out of line fixup for the ldrt above.
528 .pushsection .fixup, "ax"
531 .pushsection __ex_table,"a"
533 #if __LINUX_ARM_ARCH__ >= 7
540 * Check whether the instruction is a co-processor instruction.
541 * If yes, we need to call the relevant co-processor handler.
543 * Note that we don't do a full check here for the co-processor
544 * instructions; all instructions with bit 27 set are well
545 * defined. The only instructions that should fault are the
546 * co-processor instructions. However, we have to watch out
547 * for the ARM6/ARM7 SWI bug.
549 * NEON is a special case that has to be handled here. Not all
550 * NEON instructions are co-processor instructions, so we have
551 * to make a special case of checking for them. Plus, there's
552 * five groups of them, so we have a table of mask/opcode pairs
553 * to check against, and if any match then we branch off into the
556 * Emulators may wish to make use of the following registers:
557 * r0 = instruction opcode.
559 * r9 = normal "successful" return address
560 * r10 = this threads thread_info structure.
561 * lr = unrecognised instruction return address
564 @ Fall-through from Thumb-2 __und_usr
567 adr r6, .LCneon_thumb_opcodes
572 adr r6, .LCneon_arm_opcodes
574 ldr r7, [r6], #4 @ mask value
575 cmp r7, #0 @ end mask?
578 ldr r7, [r6], #4 @ opcode bits matching in mask
579 cmp r8, r7 @ NEON instruction?
583 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
584 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
585 b do_vfp @ let VFP handler handle this
588 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
589 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
590 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
591 and r8, r0, #0x0f000000 @ mask out op-code bits
592 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
595 get_thread_info r10 @ get current thread
596 and r8, r0, #0x00000f00 @ mask out CP number
597 THUMB( lsr r8, r8, #8 )
599 add r6, r10, #TI_USED_CP
600 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
601 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
603 @ Test if we need to give access to iWMMXt coprocessors
604 ldr r5, [r10, #TI_FLAGS]
605 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
606 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
607 bcs iwmmxt_task_enable
609 ARM( add pc, pc, r8, lsr #6 )
610 THUMB( lsl r8, r8, #2 )
615 W(b) do_fpe @ CP#1 (FPE)
616 W(b) do_fpe @ CP#2 (FPE)
619 b crunch_task_enable @ CP#4 (MaverickCrunch)
620 b crunch_task_enable @ CP#5 (MaverickCrunch)
621 b crunch_task_enable @ CP#6 (MaverickCrunch)
631 W(b) do_vfp @ CP#10 (VFP)
632 W(b) do_vfp @ CP#11 (VFP)
634 movw_pc lr @ CP#10 (VFP)
635 movw_pc lr @ CP#11 (VFP)
639 movw_pc lr @ CP#14 (Debug)
640 movw_pc lr @ CP#15 (Control)
646 .word 0xfe000000 @ mask
647 .word 0xf2000000 @ opcode
649 .word 0xff100000 @ mask
650 .word 0xf4000000 @ opcode
652 .word 0x00000000 @ mask
653 .word 0x00000000 @ opcode
655 .LCneon_thumb_opcodes:
656 .word 0xef000000 @ mask
657 .word 0xef000000 @ opcode
659 .word 0xff100000 @ mask
660 .word 0xf9000000 @ opcode
662 .word 0x00000000 @ mask
663 .word 0x00000000 @ opcode
669 add r10, r10, #TI_FPSTATE @ r10 = workspace
670 ldr pc, [r4] @ Call FP module USR entry point
673 * The FP module is called with these registers set:
676 * r9 = normal "successful" return address
678 * lr = unrecognised FP instruction return address
693 adr lr, BSYM(ret_from_exception)
695 ENDPROC(__und_usr_unknown)
701 mov r0, r2 @ pass address of aborted instruction.
705 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
707 bl CPU_PABORT_HANDLER
710 enable_irq @ Enable interrupts
712 bl do_PrefetchAbort @ call abort handler
716 * This is the return code to user mode for abort handlers
718 ENTRY(ret_from_exception)
726 ENDPROC(ret_from_exception)
729 * Register switch for ARMv3 and ARMv4 processors
730 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
731 * previous and next are guaranteed not to be the same.
736 add ip, r1, #TI_CPU_SAVE
737 ldr r3, [r2, #TI_TP_VALUE]
738 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
739 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
740 THUMB( str sp, [ip], #4 )
741 THUMB( str lr, [ip], #4 )
743 ldr r6, [r2, #TI_CPU_DOMAIN]
746 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
747 ldr r7, [r2, #TI_TASK]
748 ldr r8, =__stack_chk_guard
749 ldr r7, [r7, #TSK_STACK_CANARY]
752 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
755 add r4, r2, #TI_CPU_SAVE
756 ldr r0, =thread_notify_head
757 mov r1, #THREAD_NOTIFY_SWITCH
758 bl atomic_notifier_call_chain
759 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
764 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
765 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
766 THUMB( ldr sp, [ip], #4 )
767 THUMB( ldr pc, [ip] )
776 * These are segment of kernel provided user code reachable from user space
777 * at a fixed address in kernel memory. This is used to provide user space
778 * with some operations which require kernel help because of unimplemented
779 * native feature and/or instructions in many ARM CPUs. The idea is for
780 * this code to be executed directly in user mode for best efficiency but
781 * which is too intimate with the kernel counter part to be left to user
782 * libraries. In fact this code might even differ from one CPU to another
783 * depending on the available instruction set and restrictions like on
784 * SMP systems. In other words, the kernel reserves the right to change
785 * this code as needed without warning. Only the entry points and their
786 * results are guaranteed to be stable.
788 * Each segment is 32-byte aligned and will be moved to the top of the high
789 * vector page. New segments (if ever needed) must be added in front of
790 * existing ones. This mechanism should be used only for things that are
791 * really small and justified, and not be abused freely.
793 * User space is expected to implement those things inline when optimizing
794 * for a processor that has the necessary native support, but only if such
795 * resulting binaries are already to be incompatible with earlier ARM
796 * processors due to the use of unsupported instructions other than what
797 * is provided here. In other words don't make binaries unable to run on
798 * earlier processors just for the sake of not using these kernel helpers
799 * if your compiled code is not going to use the new instructions for other
805 #ifdef CONFIG_ARM_THUMB
813 .globl __kuser_helper_start
814 __kuser_helper_start:
817 * Reference prototype:
819 * void __kernel_memory_barrier(void)
823 * lr = return address
833 * Definition and user space usage example:
835 * typedef void (__kernel_dmb_t)(void);
836 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
838 * Apply any needed memory barrier to preserve consistency with data modified
839 * manually and __kuser_cmpxchg usage.
841 * This could be used as follows:
843 * #define __kernel_dmb() \
844 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
845 * : : : "r0", "lr","cc" )
848 __kuser_memory_barrier: @ 0xffff0fa0
855 * Reference prototype:
857 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
864 * lr = return address
868 * r0 = returned value (zero or non-zero)
869 * C flag = set if r0 == 0, clear if r0 != 0
875 * Definition and user space usage example:
877 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
878 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
880 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
881 * Return zero if *ptr was changed or non-zero if no exchange happened.
882 * The C flag is also set if *ptr was changed to allow for assembly
883 * optimization in the calling code.
887 * - This routine already includes memory barriers as needed.
889 * For example, a user space atomic_add implementation could look like this:
891 * #define atomic_add(ptr, val) \
892 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
893 * register unsigned int __result asm("r1"); \
895 * "1: @ atomic_add\n\t" \
896 * "ldr r0, [r2]\n\t" \
897 * "mov r3, #0xffff0fff\n\t" \
898 * "add lr, pc, #4\n\t" \
899 * "add r1, r0, %2\n\t" \
900 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
902 * : "=&r" (__result) \
903 * : "r" (__ptr), "rIL" (val) \
904 * : "r0","r3","ip","lr","cc","memory" ); \
908 __kuser_cmpxchg: @ 0xffff0fc0
910 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
913 * Poor you. No fast solution possible...
914 * The kernel itself must perform the operation.
915 * A special ghost syscall is used for that (see traps.c).
918 ldr r7, 1f @ it's 20 bits
921 1: .word __ARM_NR_cmpxchg
923 #elif __LINUX_ARM_ARCH__ < 6
928 * The only thing that can break atomicity in this cmpxchg
929 * implementation is either an IRQ or a data abort exception
930 * causing another process/thread to be scheduled in the middle
931 * of the critical sequence. To prevent this, code is added to
932 * the IRQ and data abort exception handlers to set the pc back
933 * to the beginning of the critical section if it is found to be
934 * within that critical section (see kuser_cmpxchg_fixup).
936 1: ldr r3, [r2] @ load current val
937 subs r3, r3, r0 @ compare with oldval
938 2: streq r1, [r2] @ store newval if eq
939 rsbs r0, r3, #0 @ set return val and C flag
944 @ Called from kuser_cmpxchg_check macro.
945 @ r2 = address of interrupted insn (must be preserved).
946 @ sp = saved regs. r7 and r8 are clobbered.
947 @ 1b = first critical insn, 2b = last critical insn.
948 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
950 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
952 rsbcss r8, r8, #(2b - 1b)
953 strcs r7, [sp, #S_PC]
958 #warning "NPTL on non MMU needs fixing"
973 /* beware -- each __kuser slot must be 8 instructions max */
974 ALT_SMP(b __kuser_memory_barrier)
982 * Reference prototype:
984 * int __kernel_get_tls(void)
988 * lr = return address
998 * Definition and user space usage example:
1000 * typedef int (__kernel_get_tls_t)(void);
1001 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1003 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1005 * This could be used as follows:
1007 * #define __kernel_get_tls() \
1008 * ({ register unsigned int __val asm("r0"); \
1009 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1010 * : "=r" (__val) : : "lr","cc" ); \
1014 __kuser_get_tls: @ 0xffff0fe0
1015 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1017 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1019 .word 0 @ 0xffff0ff0 software TLS value, then
1020 .endr @ pad up to __kuser_helper_version
1023 * Reference declaration:
1025 * extern unsigned int __kernel_helper_version;
1027 * Definition and user space usage example:
1029 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1031 * User space may read this to determine the curent number of helpers
1035 __kuser_helper_version: @ 0xffff0ffc
1036 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1038 .globl __kuser_helper_end
1046 * This code is copied to 0xffff0200 so we can use branches in the
1047 * vectors, rather than ldr's. Note that this code must not
1048 * exceed 0x300 bytes.
1050 * Common stub entry macro:
1051 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1053 * SP points to a minimal amount of processor-private memory, the address
1054 * of which is copied into r0 for the mode specific abort handler.
1056 .macro vector_stub, name, mode, correction=0
1061 sub lr, lr, #\correction
1065 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1068 stmia sp, {r0, lr} @ save r0, lr
1070 str lr, [sp, #8] @ save spsr
1073 @ Prepare for SVC32 mode. IRQs remain disabled.
1076 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1080 @ the branch table must immediately follow this code
1084 THUMB( ldr lr, [r0, lr, lsl #2] )
1086 ARM( ldr lr, [pc, lr, lsl #2] )
1087 movs pc, lr @ branch to handler in SVC mode
1088 ENDPROC(vector_\name)
1091 @ handler addresses follow this label
1095 .globl __stubs_start
1098 * Interrupt dispatcher
1100 vector_stub irq, IRQ_MODE, 4
1102 .long __irq_usr @ 0 (USR_26 / USR_32)
1103 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1104 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1105 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1106 .long __irq_invalid @ 4
1107 .long __irq_invalid @ 5
1108 .long __irq_invalid @ 6
1109 .long __irq_invalid @ 7
1110 .long __irq_invalid @ 8
1111 .long __irq_invalid @ 9
1112 .long __irq_invalid @ a
1113 .long __irq_invalid @ b
1114 .long __irq_invalid @ c
1115 .long __irq_invalid @ d
1116 .long __irq_invalid @ e
1117 .long __irq_invalid @ f
1120 * Data abort dispatcher
1121 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1123 vector_stub dabt, ABT_MODE, 8
1125 .long __dabt_usr @ 0 (USR_26 / USR_32)
1126 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1127 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1128 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1129 .long __dabt_invalid @ 4
1130 .long __dabt_invalid @ 5
1131 .long __dabt_invalid @ 6
1132 .long __dabt_invalid @ 7
1133 .long __dabt_invalid @ 8
1134 .long __dabt_invalid @ 9
1135 .long __dabt_invalid @ a
1136 .long __dabt_invalid @ b
1137 .long __dabt_invalid @ c
1138 .long __dabt_invalid @ d
1139 .long __dabt_invalid @ e
1140 .long __dabt_invalid @ f
1143 * Prefetch abort dispatcher
1144 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1146 vector_stub pabt, ABT_MODE, 4
1148 .long __pabt_usr @ 0 (USR_26 / USR_32)
1149 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1150 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1151 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1152 .long __pabt_invalid @ 4
1153 .long __pabt_invalid @ 5
1154 .long __pabt_invalid @ 6
1155 .long __pabt_invalid @ 7
1156 .long __pabt_invalid @ 8
1157 .long __pabt_invalid @ 9
1158 .long __pabt_invalid @ a
1159 .long __pabt_invalid @ b
1160 .long __pabt_invalid @ c
1161 .long __pabt_invalid @ d
1162 .long __pabt_invalid @ e
1163 .long __pabt_invalid @ f
1166 * Undef instr entry dispatcher
1167 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1169 vector_stub und, UND_MODE
1171 .long __und_usr @ 0 (USR_26 / USR_32)
1172 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1173 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1174 .long __und_svc @ 3 (SVC_26 / SVC_32)
1175 .long __und_invalid @ 4
1176 .long __und_invalid @ 5
1177 .long __und_invalid @ 6
1178 .long __und_invalid @ 7
1179 .long __und_invalid @ 8
1180 .long __und_invalid @ 9
1181 .long __und_invalid @ a
1182 .long __und_invalid @ b
1183 .long __und_invalid @ c
1184 .long __und_invalid @ d
1185 .long __und_invalid @ e
1186 .long __und_invalid @ f
1190 /*=============================================================================
1192 *-----------------------------------------------------------------------------
1193 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1194 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1195 * Basically to switch modes, we *HAVE* to clobber one register... brain
1196 * damage alert! I don't think that we can execute any code in here in any
1197 * other mode than FIQ... Ok you can switch to another mode, but you can't
1198 * get out of that mode without clobbering one register.
1204 /*=============================================================================
1205 * Address exception handler
1206 *-----------------------------------------------------------------------------
1207 * These aren't too critical.
1208 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1215 * We group all the following data together to optimise
1216 * for CPUs with separate I & D caches.
1226 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1228 .globl __vectors_start
1230 ARM( swi SYS_ERROR0 )
1233 W(b) vector_und + stubs_offset
1234 W(ldr) pc, .LCvswi + stubs_offset
1235 W(b) vector_pabt + stubs_offset
1236 W(b) vector_dabt + stubs_offset
1237 W(b) vector_addrexcptn + stubs_offset
1238 W(b) vector_irq + stubs_offset
1239 W(b) vector_fiq + stubs_offset
1241 .globl __vectors_end
1247 .globl cr_no_alignment