2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
25 #include "entry-header.S"
28 * Interrupt handling. Preserves r7, r8, r9
31 get_irqnr_preamble r5, lr
32 1: get_irqnr_and_base r0, r6, r5, lr
35 @ routine called with r0 = irq number, r1 = struct pt_regs *
44 * this macro assumes that irqstat (r6) and base (r5) are
45 * preserved from get_irqnr_and_base above
47 test_for_ipi r0, r6, r5, lr
52 #ifdef CONFIG_LOCAL_TIMERS
53 test_for_ltirq r0, r6, r5, lr
63 .section .kprobes.text,"ax",%progbits
69 * Invalid mode handlers
71 .macro inv_entry, reason
72 sub sp, sp, #S_FRAME_SIZE
73 ARM( stmib sp, {r1 - lr} )
74 THUMB( stmia sp, {r0 - r12} )
75 THUMB( str sp, [sp, #S_SP] )
76 THUMB( str lr, [sp, #S_LR] )
81 inv_entry BAD_PREFETCH
83 ENDPROC(__pabt_invalid)
88 ENDPROC(__dabt_invalid)
93 ENDPROC(__irq_invalid)
96 inv_entry BAD_UNDEFINSTR
99 @ XXX fall through to common_invalid
103 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
109 add r0, sp, #S_PC @ here for interlock avoidance
110 mov r7, #-1 @ "" "" "" ""
111 str r4, [sp] @ save preserved r0
112 stmia r0, {r5 - r7} @ lr_<exception>,
113 @ cpsr_<exception>, "old_r0"
117 ENDPROC(__und_invalid)
123 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
124 #define SPFIX(code...) code
126 #define SPFIX(code...)
129 .macro svc_entry, stack_hole=0
131 UNWIND(.save {r0 - pc} )
132 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 #ifdef CONFIG_THUMB2_KERNEL
134 SPFIX( str r0, [sp] ) @ temporarily saved
136 SPFIX( tst r0, #4 ) @ test original stack alignment
137 SPFIX( ldr r0, [sp] ) @ restored
141 SPFIX( subeq sp, sp, #4 )
145 add r5, sp, #S_SP - 4 @ here for interlock avoidance
146 mov r4, #-1 @ "" "" "" ""
147 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
148 SPFIX( addeq r0, r0, #4 )
149 str r1, [sp, #-4]! @ save the "real" r0 copied
150 @ from the exception stack
155 @ We are now ready to fill in the remaining blanks on the stack:
159 @ r2 - lr_<exception>, already fixed up for correct return/restart
160 @ r3 - spsr_<exception>
161 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
165 asm_trace_hardirqs_off
173 @ get ready to re-enable interrupts if appropriate
177 biceq r9, r9, #PSR_I_BIT
180 @ Call the processor-specific abort handler:
182 @ r2 - aborted context pc
183 @ r3 - aborted context cpsr
185 @ The abort handler must return the aborted address in r0, and
186 @ the fault status register in r1. r9 must be preserved.
191 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
193 bl CPU_DABORT_HANDLER
197 @ set desired IRQ state, then call main handler
204 @ IRQs off again before pulling preserved data off the stack
209 @ restore SPSR and restart the instruction
212 svc_exit r2 @ return from exception
220 #ifdef CONFIG_PREEMPT
222 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
223 add r7, r8, #1 @ increment it
224 str r7, [tsk, #TI_PREEMPT]
228 #ifdef CONFIG_PREEMPT
229 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
230 ldr r0, [tsk, #TI_FLAGS] @ get flags
231 teq r8, #0 @ if preempt count != 0
232 movne r0, #0 @ force flags to 0
233 tst r0, #_TIF_NEED_RESCHED
236 ldr r4, [sp, #S_PSR] @ irqs are already disabled
237 #ifdef CONFIG_TRACE_IRQFLAGS
239 bleq trace_hardirqs_on
241 svc_exit r4 @ return from exception
247 #ifdef CONFIG_PREEMPT
250 1: bl preempt_schedule_irq @ irq en/disable is done inside
251 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
252 tst r0, #_TIF_NEED_RESCHED
253 moveq pc, r8 @ go again
259 #ifdef CONFIG_KPROBES
260 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
261 @ it obviously needs free stack space which then will belong to
269 @ call emulation code, which returns using r9 if it has emulated
270 @ the instruction, or the more conventional lr if we are to treat
271 @ this as a real undefined instruction
275 #ifndef CONFIG_THUMB2_KERNEL
278 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
280 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
281 ldrhhs r9, [r2] @ bottom 16 bits
282 orrhs r0, r9, r0, lsl #16
287 mov r0, sp @ struct pt_regs *regs
291 @ IRQs off again before pulling preserved data off the stack
296 @ restore SPSR and restart the instruction
298 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
299 svc_exit r2 @ return from exception
308 @ re-enable interrupts if appropriate
312 biceq r9, r9, #PSR_I_BIT
315 @ set args, then call main handler
317 @ r0 - address of faulting instruction
318 @ r1 - pointer to registers on stack
321 mov r0, r2 @ pass address of aborted instruction.
324 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
326 CPU_PABORT_HANDLER(r0, r2)
328 msr cpsr_c, r9 @ Maybe enable interrupts
330 bl do_PrefetchAbort @ call abort handler
333 @ IRQs off again before pulling preserved data off the stack
338 @ restore SPSR and restart the instruction
341 svc_exit r2 @ return from exception
358 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
361 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
362 #error "sizeof(struct pt_regs) must be a multiple of 8"
367 UNWIND(.cantunwind ) @ don't unwind the user space
368 sub sp, sp, #S_FRAME_SIZE
369 ARM( stmib sp, {r1 - r12} )
370 THUMB( stmia sp, {r0 - r12} )
373 add r0, sp, #S_PC @ here for interlock avoidance
374 mov r4, #-1 @ "" "" "" ""
376 str r1, [sp] @ save the "real" r0 copied
377 @ from the exception stack
380 @ We are now ready to fill in the remaining blanks on the stack:
382 @ r2 - lr_<exception>, already fixed up for correct return/restart
383 @ r3 - spsr_<exception>
384 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
386 @ Also, separately save sp_usr and lr_usr
389 ARM( stmdb r0, {sp, lr}^ )
390 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
393 @ Enable the alignment trap while in kernel mode
398 @ Clear FP to mark the first stack frame
402 asm_trace_hardirqs_off
405 .macro kuser_cmpxchg_check
406 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
408 #warning "NPTL on non MMU needs fixing"
410 @ Make sure our user space atomic helper is restarted
411 @ if it was interrupted in a critical region. Here we
412 @ perform a quick test inline since it should be false
413 @ 99.9999% of the time. The rest is done out of line.
415 blhs kuser_cmpxchg_fixup
426 @ Call the processor-specific abort handler:
428 @ r2 - aborted context pc
429 @ r3 - aborted context cpsr
431 @ The abort handler must return the aborted address in r0, and
432 @ the fault status register in r1.
437 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
439 bl CPU_DABORT_HANDLER
443 @ IRQs on, then call the main handler
447 adr lr, BSYM(ret_from_exception)
458 #ifdef CONFIG_PREEMPT
459 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
460 add r7, r8, #1 @ increment it
461 str r7, [tsk, #TI_PREEMPT]
465 #ifdef CONFIG_PREEMPT
466 ldr r0, [tsk, #TI_PREEMPT]
467 str r8, [tsk, #TI_PREEMPT]
469 ARM( strne r0, [r0, -r0] )
470 THUMB( movne r0, #0 )
471 THUMB( strne r0, [r0] )
473 #ifdef CONFIG_TRACE_IRQFLAGS
489 @ fall through to the emulation code, which returns using r9 if
490 @ it has emulated the instruction, or the more conventional lr
491 @ if we are to treat this as a real undefined instruction
495 adr r9, BSYM(ret_from_exception)
496 adr lr, BSYM(__und_usr_unknown)
497 tst r3, #PSR_T_BIT @ Thumb mode?
498 itet eq @ explicit IT needed for the 1f label
499 subeq r4, r2, #4 @ ARM instr at LR - 4
500 subne r4, r2, #2 @ Thumb instr at LR - 2
502 #ifdef CONFIG_CPU_ENDIAN_BE8
503 reveq r0, r0 @ little endian instruction
507 #if __LINUX_ARM_ARCH__ >= 7
509 ARM( ldrht r5, [r4], #2 )
510 THUMB( ldrht r5, [r4] )
511 THUMB( add r4, r4, #2 )
512 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
513 cmp r0, #0xe800 @ 32bit instruction if xx != 0
514 blo __und_usr_unknown
516 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
517 orr r0, r0, r5, lsl #16
525 @ fallthrough to call_fpe
529 * The out of line fixup for the ldrt above.
531 .section .fixup, "ax"
534 .section __ex_table,"a"
536 #if __LINUX_ARM_ARCH__ >= 7
543 * Check whether the instruction is a co-processor instruction.
544 * If yes, we need to call the relevant co-processor handler.
546 * Note that we don't do a full check here for the co-processor
547 * instructions; all instructions with bit 27 set are well
548 * defined. The only instructions that should fault are the
549 * co-processor instructions. However, we have to watch out
550 * for the ARM6/ARM7 SWI bug.
552 * NEON is a special case that has to be handled here. Not all
553 * NEON instructions are co-processor instructions, so we have
554 * to make a special case of checking for them. Plus, there's
555 * five groups of them, so we have a table of mask/opcode pairs
556 * to check against, and if any match then we branch off into the
559 * Emulators may wish to make use of the following registers:
560 * r0 = instruction opcode.
562 * r9 = normal "successful" return address
563 * r10 = this threads thread_info structure.
564 * lr = unrecognised instruction return address
567 @ Fall-through from Thumb-2 __und_usr
570 adr r6, .LCneon_thumb_opcodes
575 adr r6, .LCneon_arm_opcodes
577 ldr r7, [r6], #4 @ mask value
578 cmp r7, #0 @ end mask?
581 ldr r7, [r6], #4 @ opcode bits matching in mask
582 cmp r8, r7 @ NEON instruction?
586 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
587 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
588 b do_vfp @ let VFP handler handle this
591 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
592 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
593 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
594 and r8, r0, #0x0f000000 @ mask out op-code bits
595 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
598 get_thread_info r10 @ get current thread
599 and r8, r0, #0x00000f00 @ mask out CP number
600 THUMB( lsr r8, r8, #8 )
602 add r6, r10, #TI_USED_CP
603 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
604 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
606 @ Test if we need to give access to iWMMXt coprocessors
607 ldr r5, [r10, #TI_FLAGS]
608 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
609 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
610 bcs iwmmxt_task_enable
612 ARM( add pc, pc, r8, lsr #6 )
613 THUMB( lsl r8, r8, #2 )
618 W(b) do_fpe @ CP#1 (FPE)
619 W(b) do_fpe @ CP#2 (FPE)
622 b crunch_task_enable @ CP#4 (MaverickCrunch)
623 b crunch_task_enable @ CP#5 (MaverickCrunch)
624 b crunch_task_enable @ CP#6 (MaverickCrunch)
634 W(b) do_vfp @ CP#10 (VFP)
635 W(b) do_vfp @ CP#11 (VFP)
637 W(mov) pc, lr @ CP#10 (VFP)
638 W(mov) pc, lr @ CP#11 (VFP)
640 W(mov) pc, lr @ CP#12
641 W(mov) pc, lr @ CP#13
642 W(mov) pc, lr @ CP#14 (Debug)
643 W(mov) pc, lr @ CP#15 (Control)
649 .word 0xfe000000 @ mask
650 .word 0xf2000000 @ opcode
652 .word 0xff100000 @ mask
653 .word 0xf4000000 @ opcode
655 .word 0x00000000 @ mask
656 .word 0x00000000 @ opcode
658 .LCneon_thumb_opcodes:
659 .word 0xef000000 @ mask
660 .word 0xef000000 @ opcode
662 .word 0xff100000 @ mask
663 .word 0xf9000000 @ opcode
665 .word 0x00000000 @ mask
666 .word 0x00000000 @ opcode
672 add r10, r10, #TI_FPSTATE @ r10 = workspace
673 ldr pc, [r4] @ Call FP module USR entry point
676 * The FP module is called with these registers set:
679 * r9 = normal "successful" return address
681 * lr = unrecognised FP instruction return address
696 adr lr, BSYM(ret_from_exception)
698 ENDPROC(__und_usr_unknown)
705 mov r0, r2 @ pass address of aborted instruction.
708 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
710 CPU_PABORT_HANDLER(r0, r2)
712 enable_irq @ Enable interrupts
714 bl do_PrefetchAbort @ call abort handler
718 * This is the return code to user mode for abort handlers
720 ENTRY(ret_from_exception)
728 ENDPROC(ret_from_exception)
731 * Register switch for ARMv3 and ARMv4 processors
732 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
733 * previous and next are guaranteed not to be the same.
738 add ip, r1, #TI_CPU_SAVE
739 ldr r3, [r2, #TI_TP_VALUE]
740 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
741 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
742 THUMB( str sp, [ip], #4 )
743 THUMB( str lr, [ip], #4 )
745 ldr r6, [r2, #TI_CPU_DOMAIN]
747 #if defined(CONFIG_HAS_TLS_REG)
748 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
749 #elif !defined(CONFIG_TLS_REG_EMUL)
751 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
754 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
757 add r4, r2, #TI_CPU_SAVE
758 ldr r0, =thread_notify_head
759 mov r1, #THREAD_NOTIFY_SWITCH
760 bl atomic_notifier_call_chain
763 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
764 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
765 THUMB( ldr sp, [ip], #4 )
766 THUMB( ldr pc, [ip] )
775 * These are segment of kernel provided user code reachable from user space
776 * at a fixed address in kernel memory. This is used to provide user space
777 * with some operations which require kernel help because of unimplemented
778 * native feature and/or instructions in many ARM CPUs. The idea is for
779 * this code to be executed directly in user mode for best efficiency but
780 * which is too intimate with the kernel counter part to be left to user
781 * libraries. In fact this code might even differ from one CPU to another
782 * depending on the available instruction set and restrictions like on
783 * SMP systems. In other words, the kernel reserves the right to change
784 * this code as needed without warning. Only the entry points and their
785 * results are guaranteed to be stable.
787 * Each segment is 32-byte aligned and will be moved to the top of the high
788 * vector page. New segments (if ever needed) must be added in front of
789 * existing ones. This mechanism should be used only for things that are
790 * really small and justified, and not be abused freely.
792 * User space is expected to implement those things inline when optimizing
793 * for a processor that has the necessary native support, but only if such
794 * resulting binaries are already to be incompatible with earlier ARM
795 * processors due to the use of unsupported instructions other than what
796 * is provided here. In other words don't make binaries unable to run on
797 * earlier processors just for the sake of not using these kernel helpers
798 * if your compiled code is not going to use the new instructions for other
804 #ifdef CONFIG_ARM_THUMB
812 .globl __kuser_helper_start
813 __kuser_helper_start:
816 * Reference prototype:
818 * void __kernel_memory_barrier(void)
822 * lr = return address
832 * Definition and user space usage example:
834 * typedef void (__kernel_dmb_t)(void);
835 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
837 * Apply any needed memory barrier to preserve consistency with data modified
838 * manually and __kuser_cmpxchg usage.
840 * This could be used as follows:
842 * #define __kernel_dmb() \
843 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
844 * : : : "r0", "lr","cc" )
847 __kuser_memory_barrier: @ 0xffff0fa0
854 * Reference prototype:
856 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
863 * lr = return address
867 * r0 = returned value (zero or non-zero)
868 * C flag = set if r0 == 0, clear if r0 != 0
874 * Definition and user space usage example:
876 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
877 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
879 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
880 * Return zero if *ptr was changed or non-zero if no exchange happened.
881 * The C flag is also set if *ptr was changed to allow for assembly
882 * optimization in the calling code.
886 * - This routine already includes memory barriers as needed.
888 * For example, a user space atomic_add implementation could look like this:
890 * #define atomic_add(ptr, val) \
891 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
892 * register unsigned int __result asm("r1"); \
894 * "1: @ atomic_add\n\t" \
895 * "ldr r0, [r2]\n\t" \
896 * "mov r3, #0xffff0fff\n\t" \
897 * "add lr, pc, #4\n\t" \
898 * "add r1, r0, %2\n\t" \
899 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
901 * : "=&r" (__result) \
902 * : "r" (__ptr), "rIL" (val) \
903 * : "r0","r3","ip","lr","cc","memory" ); \
907 __kuser_cmpxchg: @ 0xffff0fc0
909 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
912 * Poor you. No fast solution possible...
913 * The kernel itself must perform the operation.
914 * A special ghost syscall is used for that (see traps.c).
917 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
922 #elif __LINUX_ARM_ARCH__ < 6
927 * The only thing that can break atomicity in this cmpxchg
928 * implementation is either an IRQ or a data abort exception
929 * causing another process/thread to be scheduled in the middle
930 * of the critical sequence. To prevent this, code is added to
931 * the IRQ and data abort exception handlers to set the pc back
932 * to the beginning of the critical section if it is found to be
933 * within that critical section (see kuser_cmpxchg_fixup).
935 1: ldr r3, [r2] @ load current val
936 subs r3, r3, r0 @ compare with oldval
937 2: streq r1, [r2] @ store newval if eq
938 rsbs r0, r3, #0 @ set return val and C flag
943 @ Called from kuser_cmpxchg_check macro.
944 @ r2 = address of interrupted insn (must be preserved).
945 @ sp = saved regs. r7 and r8 are clobbered.
946 @ 1b = first critical insn, 2b = last critical insn.
947 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
949 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
951 rsbcss r8, r8, #(2b - 1b)
952 strcs r7, [sp, #S_PC]
957 #warning "NPTL on non MMU needs fixing"
966 mcr p15, 0, r0, c7, c10, 5 @ dmb
974 /* beware -- each __kuser slot must be 8 instructions max */
976 b __kuser_memory_barrier
986 * Reference prototype:
988 * int __kernel_get_tls(void)
992 * lr = return address
1002 * Definition and user space usage example:
1004 * typedef int (__kernel_get_tls_t)(void);
1005 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1007 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1009 * This could be used as follows:
1011 * #define __kernel_get_tls() \
1012 * ({ register unsigned int __val asm("r0"); \
1013 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1014 * : "=r" (__val) : : "lr","cc" ); \
1018 __kuser_get_tls: @ 0xffff0fe0
1020 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1021 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1023 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1028 .word 0 @ pad up to __kuser_helper_version
1032 * Reference declaration:
1034 * extern unsigned int __kernel_helper_version;
1036 * Definition and user space usage example:
1038 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1040 * User space may read this to determine the curent number of helpers
1044 __kuser_helper_version: @ 0xffff0ffc
1045 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1047 .globl __kuser_helper_end
1055 * This code is copied to 0xffff0200 so we can use branches in the
1056 * vectors, rather than ldr's. Note that this code must not
1057 * exceed 0x300 bytes.
1059 * Common stub entry macro:
1060 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1062 * SP points to a minimal amount of processor-private memory, the address
1063 * of which is copied into r0 for the mode specific abort handler.
1065 .macro vector_stub, name, mode, correction=0
1070 sub lr, lr, #\correction
1074 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1077 stmia sp, {r0, lr} @ save r0, lr
1079 str lr, [sp, #8] @ save spsr
1082 @ Prepare for SVC32 mode. IRQs remain disabled.
1085 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1089 @ the branch table must immediately follow this code
1093 THUMB( ldr lr, [r0, lr, lsl #2] )
1095 ARM( ldr lr, [pc, lr, lsl #2] )
1096 movs pc, lr @ branch to handler in SVC mode
1097 ENDPROC(vector_\name)
1100 @ handler addresses follow this label
1104 .globl __stubs_start
1107 * Interrupt dispatcher
1109 vector_stub irq, IRQ_MODE, 4
1111 .long __irq_usr @ 0 (USR_26 / USR_32)
1112 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1113 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1114 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1115 .long __irq_invalid @ 4
1116 .long __irq_invalid @ 5
1117 .long __irq_invalid @ 6
1118 .long __irq_invalid @ 7
1119 .long __irq_invalid @ 8
1120 .long __irq_invalid @ 9
1121 .long __irq_invalid @ a
1122 .long __irq_invalid @ b
1123 .long __irq_invalid @ c
1124 .long __irq_invalid @ d
1125 .long __irq_invalid @ e
1126 .long __irq_invalid @ f
1129 * Data abort dispatcher
1130 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1132 vector_stub dabt, ABT_MODE, 8
1134 .long __dabt_usr @ 0 (USR_26 / USR_32)
1135 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1136 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1137 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1138 .long __dabt_invalid @ 4
1139 .long __dabt_invalid @ 5
1140 .long __dabt_invalid @ 6
1141 .long __dabt_invalid @ 7
1142 .long __dabt_invalid @ 8
1143 .long __dabt_invalid @ 9
1144 .long __dabt_invalid @ a
1145 .long __dabt_invalid @ b
1146 .long __dabt_invalid @ c
1147 .long __dabt_invalid @ d
1148 .long __dabt_invalid @ e
1149 .long __dabt_invalid @ f
1152 * Prefetch abort dispatcher
1153 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1155 vector_stub pabt, ABT_MODE, 4
1157 .long __pabt_usr @ 0 (USR_26 / USR_32)
1158 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1159 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1160 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1161 .long __pabt_invalid @ 4
1162 .long __pabt_invalid @ 5
1163 .long __pabt_invalid @ 6
1164 .long __pabt_invalid @ 7
1165 .long __pabt_invalid @ 8
1166 .long __pabt_invalid @ 9
1167 .long __pabt_invalid @ a
1168 .long __pabt_invalid @ b
1169 .long __pabt_invalid @ c
1170 .long __pabt_invalid @ d
1171 .long __pabt_invalid @ e
1172 .long __pabt_invalid @ f
1175 * Undef instr entry dispatcher
1176 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1178 vector_stub und, UND_MODE
1180 .long __und_usr @ 0 (USR_26 / USR_32)
1181 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1182 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1183 .long __und_svc @ 3 (SVC_26 / SVC_32)
1184 .long __und_invalid @ 4
1185 .long __und_invalid @ 5
1186 .long __und_invalid @ 6
1187 .long __und_invalid @ 7
1188 .long __und_invalid @ 8
1189 .long __und_invalid @ 9
1190 .long __und_invalid @ a
1191 .long __und_invalid @ b
1192 .long __und_invalid @ c
1193 .long __und_invalid @ d
1194 .long __und_invalid @ e
1195 .long __und_invalid @ f
1199 /*=============================================================================
1201 *-----------------------------------------------------------------------------
1202 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1203 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1204 * Basically to switch modes, we *HAVE* to clobber one register... brain
1205 * damage alert! I don't think that we can execute any code in here in any
1206 * other mode than FIQ... Ok you can switch to another mode, but you can't
1207 * get out of that mode without clobbering one register.
1213 /*=============================================================================
1214 * Address exception handler
1215 *-----------------------------------------------------------------------------
1216 * These aren't too critical.
1217 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1224 * We group all the following data together to optimise
1225 * for CPUs with separate I & D caches.
1235 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1237 .globl __vectors_start
1239 ARM( swi SYS_ERROR0 )
1242 W(b) vector_und + stubs_offset
1243 W(ldr) pc, .LCvswi + stubs_offset
1244 W(b) vector_pabt + stubs_offset
1245 W(b) vector_dabt + stubs_offset
1246 W(b) vector_addrexcptn + stubs_offset
1247 W(b) vector_irq + stubs_offset
1248 W(b) vector_fiq + stubs_offset
1250 .globl __vectors_end
1256 .globl cr_no_alignment