2 * arch/arm/kernel/kprobes-decode.c
4 * Copyright (C) 2006, 2007 Motorola Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
17 * We do not have hardware single-stepping on ARM, This
18 * effort is further complicated by the ARM not having a
19 * "next PC" register. Instructions that change the PC
20 * can't be safely single-stepped in a MP environment, so
21 * we have a lot of work to do:
23 * In the prepare phase:
24 * *) If it is an instruction that does anything
25 * with the CPU mode, we reject it for a kprobe.
26 * (This is out of laziness rather than need. The
27 * instructions could be simulated.)
29 * *) Otherwise, decode the instruction rewriting its
30 * registers to take fixed, ordered registers and
31 * setting a handler for it to run the instruction.
33 * In the execution phase by an instruction's handler:
35 * *) If the PC is written to by the instruction, the
36 * instruction must be fully simulated in software.
37 * If it is a conditional instruction, the handler
38 * will use insn[0] to copy its condition code to
39 * set r0 to 1 and insn[1] to "mov pc, lr" to return.
41 * *) Otherwise, a modified form of the instruction is
42 * directly executed. Its handler calls the
43 * instruction in insn[0]. In insn[1] is a
44 * "mov pc, lr" to return.
46 * Before calling, load up the reordered registers
47 * from the original instruction's registers. If one
48 * of the original input registers is the PC, compute
49 * and adjust the appropriate input register.
51 * After call completes, copy the output registers to
52 * the original instruction's original registers.
54 * We don't use a real breakpoint instruction since that
55 * would have us in the kernel go from SVC mode to SVC
56 * mode losing the link register. Instead we use an
57 * undefined instruction. To simplify processing, the
58 * undefined instruction used for kprobes must be reserved
59 * exclusively for kprobes use.
61 * TODO: ifdef out some instruction decoding based on architecture.
64 #include <linux/kernel.h>
65 #include <linux/kprobes.h>
67 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
69 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
71 #define PSR_fs (PSR_f|PSR_s)
73 #define KPROBE_RETURN_INSTRUCTION 0xe1a0f00e /* mov pc, lr */
74 #define SET_R0_TRUE_INSTRUCTION 0xe3a00001 /* mov r0, #1 */
76 #define truecc_insn(insn) (((insn) & 0xf0000000) | \
77 (SET_R0_TRUE_INSTRUCTION & 0x0fffffff))
79 typedef long (insn_0arg_fn_t)(void);
80 typedef long (insn_1arg_fn_t)(long);
81 typedef long (insn_2arg_fn_t)(long, long);
82 typedef long (insn_3arg_fn_t)(long, long, long);
83 typedef long (insn_4arg_fn_t)(long, long, long, long);
84 typedef long long (insn_llret_0arg_fn_t)(void);
85 typedef long long (insn_llret_3arg_fn_t)(long, long, long);
86 typedef long long (insn_llret_4arg_fn_t)(long, long, long, long);
90 #ifdef __LITTLE_ENDIAN
91 struct { long r0, r1; };
93 struct { long r1, r0; };
98 * For STR and STM instructions, an ARM core may choose to use either
99 * a +8 or a +12 displacement from the current instruction's address.
100 * Whichever value is chosen for a given core, it must be the same for
101 * both instructions and may not change. This function measures it.
104 static int str_pc_offset;
106 static void __init find_str_pc_offset(void)
108 int addr, scratch, ret;
111 "sub %[ret], pc, #4 \n\t"
112 "str pc, %[addr] \n\t"
113 "ldr %[scr], %[addr] \n\t"
114 "sub %[ret], %[scr], %[ret] \n\t"
115 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
121 * The insnslot_?arg_r[w]flags() functions below are to keep the
122 * msr -> *fn -> mrs instruction sequences indivisible so that
123 * the state of the CPSR flags aren't inadvertently modified
124 * just before or just after the call.
127 static inline long __kprobes
128 insnslot_0arg_rflags(long cpsr, insn_0arg_fn_t *fn)
130 register long ret asm("r0");
132 __asm__ __volatile__ (
133 "msr cpsr_fs, %[cpsr] \n\t"
137 : [cpsr] "r" (cpsr), [fn] "r" (fn)
143 static inline long long __kprobes
144 insnslot_llret_0arg_rflags(long cpsr, insn_llret_0arg_fn_t *fn)
146 register long ret0 asm("r0");
147 register long ret1 asm("r1");
150 __asm__ __volatile__ (
151 "msr cpsr_fs, %[cpsr] \n\t"
154 : "=r" (ret0), "=r" (ret1)
155 : [cpsr] "r" (cpsr), [fn] "r" (fn)
163 static inline long __kprobes
164 insnslot_1arg_rflags(long r0, long cpsr, insn_1arg_fn_t *fn)
166 register long rr0 asm("r0") = r0;
167 register long ret asm("r0");
169 __asm__ __volatile__ (
170 "msr cpsr_fs, %[cpsr] \n\t"
174 : "0" (rr0), [cpsr] "r" (cpsr), [fn] "r" (fn)
180 static inline long __kprobes
181 insnslot_2arg_rflags(long r0, long r1, long cpsr, insn_2arg_fn_t *fn)
183 register long rr0 asm("r0") = r0;
184 register long rr1 asm("r1") = r1;
185 register long ret asm("r0");
187 __asm__ __volatile__ (
188 "msr cpsr_fs, %[cpsr] \n\t"
192 : "0" (rr0), "r" (rr1),
193 [cpsr] "r" (cpsr), [fn] "r" (fn)
199 static inline long __kprobes
200 insnslot_3arg_rflags(long r0, long r1, long r2, long cpsr, insn_3arg_fn_t *fn)
202 register long rr0 asm("r0") = r0;
203 register long rr1 asm("r1") = r1;
204 register long rr2 asm("r2") = r2;
205 register long ret asm("r0");
207 __asm__ __volatile__ (
208 "msr cpsr_fs, %[cpsr] \n\t"
212 : "0" (rr0), "r" (rr1), "r" (rr2),
213 [cpsr] "r" (cpsr), [fn] "r" (fn)
219 static inline long long __kprobes
220 insnslot_llret_3arg_rflags(long r0, long r1, long r2, long cpsr,
221 insn_llret_3arg_fn_t *fn)
223 register long rr0 asm("r0") = r0;
224 register long rr1 asm("r1") = r1;
225 register long rr2 asm("r2") = r2;
226 register long ret0 asm("r0");
227 register long ret1 asm("r1");
230 __asm__ __volatile__ (
231 "msr cpsr_fs, %[cpsr] \n\t"
234 : "=r" (ret0), "=r" (ret1)
235 : "0" (rr0), "r" (rr1), "r" (rr2),
236 [cpsr] "r" (cpsr), [fn] "r" (fn)
244 static inline long __kprobes
245 insnslot_4arg_rflags(long r0, long r1, long r2, long r3, long cpsr,
248 register long rr0 asm("r0") = r0;
249 register long rr1 asm("r1") = r1;
250 register long rr2 asm("r2") = r2;
251 register long rr3 asm("r3") = r3;
252 register long ret asm("r0");
254 __asm__ __volatile__ (
255 "msr cpsr_fs, %[cpsr] \n\t"
259 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
260 [cpsr] "r" (cpsr), [fn] "r" (fn)
266 static inline long __kprobes
267 insnslot_1arg_rwflags(long r0, long *cpsr, insn_1arg_fn_t *fn)
269 register long rr0 asm("r0") = r0;
270 register long ret asm("r0");
271 long oldcpsr = *cpsr;
274 __asm__ __volatile__ (
275 "msr cpsr_fs, %[oldcpsr] \n\t"
278 "mrs %[newcpsr], cpsr \n\t"
279 : "=r" (ret), [newcpsr] "=r" (newcpsr)
280 : "0" (rr0), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
283 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
287 static inline long __kprobes
288 insnslot_2arg_rwflags(long r0, long r1, long *cpsr, insn_2arg_fn_t *fn)
290 register long rr0 asm("r0") = r0;
291 register long rr1 asm("r1") = r1;
292 register long ret asm("r0");
293 long oldcpsr = *cpsr;
296 __asm__ __volatile__ (
297 "msr cpsr_fs, %[oldcpsr] \n\t"
300 "mrs %[newcpsr], cpsr \n\t"
301 : "=r" (ret), [newcpsr] "=r" (newcpsr)
302 : "0" (rr0), "r" (rr1), [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
305 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
309 static inline long __kprobes
310 insnslot_3arg_rwflags(long r0, long r1, long r2, long *cpsr,
313 register long rr0 asm("r0") = r0;
314 register long rr1 asm("r1") = r1;
315 register long rr2 asm("r2") = r2;
316 register long ret asm("r0");
317 long oldcpsr = *cpsr;
320 __asm__ __volatile__ (
321 "msr cpsr_fs, %[oldcpsr] \n\t"
324 "mrs %[newcpsr], cpsr \n\t"
325 : "=r" (ret), [newcpsr] "=r" (newcpsr)
326 : "0" (rr0), "r" (rr1), "r" (rr2),
327 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
330 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
334 static inline long __kprobes
335 insnslot_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
338 register long rr0 asm("r0") = r0;
339 register long rr1 asm("r1") = r1;
340 register long rr2 asm("r2") = r2;
341 register long rr3 asm("r3") = r3;
342 register long ret asm("r0");
343 long oldcpsr = *cpsr;
346 __asm__ __volatile__ (
347 "msr cpsr_fs, %[oldcpsr] \n\t"
350 "mrs %[newcpsr], cpsr \n\t"
351 : "=r" (ret), [newcpsr] "=r" (newcpsr)
352 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
353 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
356 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
360 static inline long long __kprobes
361 insnslot_llret_4arg_rwflags(long r0, long r1, long r2, long r3, long *cpsr,
362 insn_llret_4arg_fn_t *fn)
364 register long rr0 asm("r0") = r0;
365 register long rr1 asm("r1") = r1;
366 register long rr2 asm("r2") = r2;
367 register long rr3 asm("r3") = r3;
368 register long ret0 asm("r0");
369 register long ret1 asm("r1");
370 long oldcpsr = *cpsr;
374 __asm__ __volatile__ (
375 "msr cpsr_fs, %[oldcpsr] \n\t"
378 "mrs %[newcpsr], cpsr \n\t"
379 : "=r" (ret0), "=r" (ret1), [newcpsr] "=r" (newcpsr)
380 : "0" (rr0), "r" (rr1), "r" (rr2), "r" (rr3),
381 [oldcpsr] "r" (oldcpsr), [fn] "r" (fn)
384 *cpsr = (oldcpsr & ~PSR_fs) | (newcpsr & PSR_fs);
391 * To avoid the complications of mimicing single-stepping on a
392 * processor without a Next-PC or a single-step mode, and to
393 * avoid having to deal with the side-effects of boosting, we
394 * simulate or emulate (almost) all ARM instructions.
396 * "Simulation" is where the instruction's behavior is duplicated in
397 * C code. "Emulation" is where the original instruction is rewritten
398 * and executed, often by altering its registers.
400 * By having all behavior of the kprobe'd instruction completed before
401 * returning from the kprobe_handler(), all locks (scheduler and
402 * interrupt) can safely be released. There is no need for secondary
403 * breakpoints, no race with MP or preemptable kernels, nor having to
404 * clean up resources counts at a later time impacting overall system
405 * performance. By rewriting the instruction, only the minimum registers
406 * need to be loaded and saved back optimizing performance.
408 * Calling the insnslot_*_rwflags version of a function doesn't hurt
409 * anything even when the CPSR flags aren't updated by the
410 * instruction. It's just a little slower in return for saving
411 * a little space by not having a duplicate function that doesn't
412 * update the flags. (The same optimization can be said for
413 * instructions that do or don't perform register writeback)
414 * Also, instructions can either read the flags, only write the
415 * flags, or read and write the flags. To save combinations
416 * rather than for sheer performance, flag functions just assume
417 * read and write of flags.
420 static void __kprobes simulate_bbl(struct kprobe *p, struct pt_regs *regs)
422 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
423 kprobe_opcode_t insn = p->opcode;
424 long iaddr = (long)p->addr;
425 int disp = branch_displacement(insn);
427 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
430 if (insn & (1 << 24))
431 regs->ARM_lr = iaddr + 4;
433 regs->ARM_pc = iaddr + 8 + disp;
436 static void __kprobes simulate_blx1(struct kprobe *p, struct pt_regs *regs)
438 kprobe_opcode_t insn = p->opcode;
439 long iaddr = (long)p->addr;
440 int disp = branch_displacement(insn);
442 regs->ARM_lr = iaddr + 4;
443 regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
444 regs->ARM_cpsr |= PSR_T_BIT;
447 static void __kprobes simulate_blx2bx(struct kprobe *p, struct pt_regs *regs)
449 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
450 kprobe_opcode_t insn = p->opcode;
452 long rmv = regs->uregs[rm];
454 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
458 regs->ARM_lr = (long)p->addr + 4;
460 regs->ARM_pc = rmv & ~0x1;
461 regs->ARM_cpsr &= ~PSR_T_BIT;
463 regs->ARM_cpsr |= PSR_T_BIT;
466 static void __kprobes simulate_ldm1stm1(struct kprobe *p, struct pt_regs *regs)
468 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
469 kprobe_opcode_t insn = p->opcode;
470 int rn = (insn >> 16) & 0xf;
471 int lbit = insn & (1 << 20);
472 int wbit = insn & (1 << 21);
473 int ubit = insn & (1 << 23);
474 int pbit = insn & (1 << 24);
475 long *addr = (long *)regs->uregs[rn];
479 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
483 reg_bit_vector = insn & 0xffff;
484 while (reg_bit_vector) {
485 reg_bit_vector &= (reg_bit_vector - 1);
491 addr += (!pbit == !ubit);
493 reg_bit_vector = insn & 0xffff;
494 while (reg_bit_vector) {
495 int reg = __ffs(reg_bit_vector);
496 reg_bit_vector &= (reg_bit_vector - 1);
498 regs->uregs[reg] = *addr++;
500 *addr++ = regs->uregs[reg];
506 addr -= (!pbit == !ubit);
507 regs->uregs[rn] = (long)addr;
511 static void __kprobes simulate_stm1_pc(struct kprobe *p, struct pt_regs *regs)
513 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
515 if (!insnslot_1arg_rflags(0, regs->ARM_cpsr, i_fn))
518 regs->ARM_pc = (long)p->addr + str_pc_offset;
519 simulate_ldm1stm1(p, regs);
520 regs->ARM_pc = (long)p->addr + 4;
523 static void __kprobes simulate_mov_ipsp(struct kprobe *p, struct pt_regs *regs)
525 regs->uregs[12] = regs->uregs[13];
528 static void __kprobes emulate_ldcstc(struct kprobe *p, struct pt_regs *regs)
530 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
531 kprobe_opcode_t insn = p->opcode;
532 int rn = (insn >> 16) & 0xf;
533 long rnv = regs->uregs[rn];
535 /* Save Rn in case of writeback. */
536 regs->uregs[rn] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
539 static void __kprobes emulate_ldrd(struct kprobe *p, struct pt_regs *regs)
541 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
542 kprobe_opcode_t insn = p->opcode;
543 int rd = (insn >> 12) & 0xf;
544 int rn = (insn >> 16) & 0xf;
545 int rm = insn & 0xf; /* rm may be invalid, don't care. */
547 /* Not following the C calling convention here, so need asm(). */
548 __asm__ __volatile__ (
551 "msr cpsr_fs, %[cpsr]\n\t"
553 "mov pc, %[i_fn] \n\t"
554 "str r0, %[rn] \n\t" /* in case of writeback */
555 "str r2, %[rd0] \n\t"
556 "str r3, %[rd1] \n\t"
557 : [rn] "+m" (regs->uregs[rn]),
558 [rd0] "=m" (regs->uregs[rd]),
559 [rd1] "=m" (regs->uregs[rd+1])
560 : [rm] "m" (regs->uregs[rm]),
561 [cpsr] "r" (regs->ARM_cpsr),
563 : "r0", "r1", "r2", "r3", "lr", "cc"
567 static void __kprobes emulate_strd(struct kprobe *p, struct pt_regs *regs)
569 insn_4arg_fn_t *i_fn = (insn_4arg_fn_t *)&p->ainsn.insn[0];
570 kprobe_opcode_t insn = p->opcode;
571 int rd = (insn >> 12) & 0xf;
572 int rn = (insn >> 16) & 0xf;
574 long rnv = regs->uregs[rn];
575 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
577 regs->uregs[rn] = insnslot_4arg_rflags(rnv, rmv, regs->uregs[rd],
579 regs->ARM_cpsr, i_fn);
582 static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
584 insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
585 kprobe_opcode_t insn = p->opcode;
586 long ppc = (long)p->addr + 8;
588 int rd = (insn >> 12) & 0xf;
589 int rn = (insn >> 16) & 0xf;
592 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
593 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
594 long cpsr = regs->ARM_cpsr;
596 fnr.dr = insnslot_llret_3arg_rflags(rnv, 0, rmv, cpsr, i_fn);
598 regs->uregs[rn] = fnr.r0; /* Save Rn in case of writeback. */
602 #if __LINUX_ARM_ARCH__ >= 5
606 regs->ARM_cpsr = cpsr;
612 regs->uregs[rd] = rdv;
615 static void __kprobes emulate_str(struct kprobe *p, struct pt_regs *regs)
617 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
618 kprobe_opcode_t insn = p->opcode;
619 long iaddr = (long)p->addr;
620 int rd = (insn >> 12) & 0xf;
621 int rn = (insn >> 16) & 0xf;
623 long rdv = (rd == 15) ? iaddr + str_pc_offset : regs->uregs[rd];
624 long rnv = (rn == 15) ? iaddr + 8 : regs->uregs[rn];
625 long rmv = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
628 rnv_wb = insnslot_3arg_rflags(rnv, rdv, rmv, regs->ARM_cpsr, i_fn);
630 regs->uregs[rn] = rnv_wb; /* Save Rn in case of writeback. */
633 static void __kprobes emulate_mrrc(struct kprobe *p, struct pt_regs *regs)
635 insn_llret_0arg_fn_t *i_fn = (insn_llret_0arg_fn_t *)&p->ainsn.insn[0];
636 kprobe_opcode_t insn = p->opcode;
638 int rd = (insn >> 12) & 0xf;
639 int rn = (insn >> 16) & 0xf;
641 fnr.dr = insnslot_llret_0arg_rflags(regs->ARM_cpsr, i_fn);
642 regs->uregs[rn] = fnr.r0;
643 regs->uregs[rd] = fnr.r1;
646 static void __kprobes emulate_mcrr(struct kprobe *p, struct pt_regs *regs)
648 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
649 kprobe_opcode_t insn = p->opcode;
650 int rd = (insn >> 12) & 0xf;
651 int rn = (insn >> 16) & 0xf;
652 long rnv = regs->uregs[rn];
653 long rdv = regs->uregs[rd];
655 insnslot_2arg_rflags(rnv, rdv, regs->ARM_cpsr, i_fn);
658 static void __kprobes emulate_sat(struct kprobe *p, struct pt_regs *regs)
660 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
661 kprobe_opcode_t insn = p->opcode;
662 int rd = (insn >> 12) & 0xf;
664 long rmv = regs->uregs[rm];
667 regs->uregs[rd] = insnslot_1arg_rwflags(rmv, ®s->ARM_cpsr, i_fn);
670 static void __kprobes emulate_sel(struct kprobe *p, struct pt_regs *regs)
672 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
673 kprobe_opcode_t insn = p->opcode;
674 int rd = (insn >> 12) & 0xf;
675 int rn = (insn >> 16) & 0xf;
677 long rnv = regs->uregs[rn];
678 long rmv = regs->uregs[rm];
681 regs->uregs[rd] = insnslot_2arg_rflags(rnv, rmv, regs->ARM_cpsr, i_fn);
684 static void __kprobes emulate_none(struct kprobe *p, struct pt_regs *regs)
686 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
688 insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
691 static void __kprobes emulate_rd12(struct kprobe *p, struct pt_regs *regs)
693 insn_0arg_fn_t *i_fn = (insn_0arg_fn_t *)&p->ainsn.insn[0];
694 kprobe_opcode_t insn = p->opcode;
695 int rd = (insn >> 12) & 0xf;
697 regs->uregs[rd] = insnslot_0arg_rflags(regs->ARM_cpsr, i_fn);
700 static void __kprobes emulate_ird12(struct kprobe *p, struct pt_regs *regs)
702 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
703 kprobe_opcode_t insn = p->opcode;
704 int ird = (insn >> 12) & 0xf;
706 insnslot_1arg_rflags(regs->uregs[ird], regs->ARM_cpsr, i_fn);
709 static void __kprobes emulate_rn16(struct kprobe *p, struct pt_regs *regs)
711 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
712 kprobe_opcode_t insn = p->opcode;
713 int rn = (insn >> 16) & 0xf;
714 long rnv = regs->uregs[rn];
716 insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
719 static void __kprobes emulate_rd12rm0(struct kprobe *p, struct pt_regs *regs)
721 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
722 kprobe_opcode_t insn = p->opcode;
723 int rd = (insn >> 12) & 0xf;
725 long rmv = regs->uregs[rm];
727 regs->uregs[rd] = insnslot_1arg_rflags(rmv, regs->ARM_cpsr, i_fn);
730 static void __kprobes
731 emulate_rd12rn16rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
733 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
734 kprobe_opcode_t insn = p->opcode;
735 int rd = (insn >> 12) & 0xf;
736 int rn = (insn >> 16) & 0xf;
738 long rnv = regs->uregs[rn];
739 long rmv = regs->uregs[rm];
742 insnslot_2arg_rwflags(rnv, rmv, ®s->ARM_cpsr, i_fn);
745 static void __kprobes
746 emulate_rd16rn12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
748 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
749 kprobe_opcode_t insn = p->opcode;
750 int rd = (insn >> 16) & 0xf;
751 int rn = (insn >> 12) & 0xf;
752 int rs = (insn >> 8) & 0xf;
754 long rnv = regs->uregs[rn];
755 long rsv = regs->uregs[rs];
756 long rmv = regs->uregs[rm];
759 insnslot_3arg_rwflags(rnv, rsv, rmv, ®s->ARM_cpsr, i_fn);
762 static void __kprobes
763 emulate_rd16rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
765 insn_2arg_fn_t *i_fn = (insn_2arg_fn_t *)&p->ainsn.insn[0];
766 kprobe_opcode_t insn = p->opcode;
767 int rd = (insn >> 16) & 0xf;
768 int rs = (insn >> 8) & 0xf;
770 long rsv = regs->uregs[rs];
771 long rmv = regs->uregs[rm];
774 insnslot_2arg_rwflags(rsv, rmv, ®s->ARM_cpsr, i_fn);
777 static void __kprobes
778 emulate_rdhi16rdlo12rs8rm0_rwflags(struct kprobe *p, struct pt_regs *regs)
780 insn_llret_4arg_fn_t *i_fn = (insn_llret_4arg_fn_t *)&p->ainsn.insn[0];
781 kprobe_opcode_t insn = p->opcode;
783 int rdhi = (insn >> 16) & 0xf;
784 int rdlo = (insn >> 12) & 0xf;
785 int rs = (insn >> 8) & 0xf;
787 long rsv = regs->uregs[rs];
788 long rmv = regs->uregs[rm];
790 fnr.dr = insnslot_llret_4arg_rwflags(regs->uregs[rdhi],
791 regs->uregs[rdlo], rsv, rmv,
792 ®s->ARM_cpsr, i_fn);
793 regs->uregs[rdhi] = fnr.r0;
794 regs->uregs[rdlo] = fnr.r1;
797 static void __kprobes
798 emulate_alu_imm_rflags(struct kprobe *p, struct pt_regs *regs)
800 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
801 kprobe_opcode_t insn = p->opcode;
802 int rd = (insn >> 12) & 0xf;
803 int rn = (insn >> 16) & 0xf;
804 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
806 regs->uregs[rd] = insnslot_1arg_rflags(rnv, regs->ARM_cpsr, i_fn);
809 static void __kprobes
810 emulate_alu_imm_rwflags(struct kprobe *p, struct pt_regs *regs)
812 insn_1arg_fn_t *i_fn = (insn_1arg_fn_t *)&p->ainsn.insn[0];
813 kprobe_opcode_t insn = p->opcode;
814 int rd = (insn >> 12) & 0xf;
815 int rn = (insn >> 16) & 0xf;
816 long rnv = (rn == 15) ? (long)p->addr + 8 : regs->uregs[rn];
818 regs->uregs[rd] = insnslot_1arg_rwflags(rnv, ®s->ARM_cpsr, i_fn);
821 static void __kprobes
822 emulate_alu_rflags(struct kprobe *p, struct pt_regs *regs)
824 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
825 kprobe_opcode_t insn = p->opcode;
826 long ppc = (long)p->addr + 8;
827 int rd = (insn >> 12) & 0xf;
828 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
829 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
831 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
832 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
833 long rsv = regs->uregs[rs];
836 insnslot_3arg_rflags(rnv, rmv, rsv, regs->ARM_cpsr, i_fn);
839 static void __kprobes
840 emulate_alu_rwflags(struct kprobe *p, struct pt_regs *regs)
842 insn_3arg_fn_t *i_fn = (insn_3arg_fn_t *)&p->ainsn.insn[0];
843 kprobe_opcode_t insn = p->opcode;
844 long ppc = (long)p->addr + 8;
845 int rd = (insn >> 12) & 0xf;
846 int rn = (insn >> 16) & 0xf; /* rn/rnv/rs/rsv may be */
847 int rs = (insn >> 8) & 0xf; /* invalid, don't care. */
849 long rnv = (rn == 15) ? ppc : regs->uregs[rn];
850 long rmv = (rm == 15) ? ppc : regs->uregs[rm];
851 long rsv = regs->uregs[rs];
854 insnslot_3arg_rwflags(rnv, rmv, rsv, ®s->ARM_cpsr, i_fn);
857 static enum kprobe_insn __kprobes
858 prep_emulate_ldr_str(kprobe_opcode_t insn, struct arch_specific_insn *asi)
860 int ibit = (insn & (1 << 26)) ? 25 : 22;
863 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
864 if (insn & (1 << ibit)) {
866 insn |= 2; /* Rm = r2 */
869 asi->insn_handler = (insn & (1 << 20)) ? emulate_ldr : emulate_str;
873 static enum kprobe_insn __kprobes
874 prep_emulate_rd12rm0(kprobe_opcode_t insn, struct arch_specific_insn *asi)
876 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
878 asi->insn_handler = emulate_rd12rm0;
882 static enum kprobe_insn __kprobes
883 prep_emulate_rd12(kprobe_opcode_t insn, struct arch_specific_insn *asi)
885 insn &= 0xffff0fff; /* Rd = r0 */
887 asi->insn_handler = emulate_rd12;
891 static enum kprobe_insn __kprobes
892 prep_emulate_rd12rn16rm0_wflags(kprobe_opcode_t insn,
893 struct arch_specific_insn *asi)
895 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
896 insn |= 0x00000001; /* Rm = r1 */
898 asi->insn_handler = emulate_rd12rn16rm0_rwflags;
902 static enum kprobe_insn __kprobes
903 prep_emulate_rd16rs8rm0_wflags(kprobe_opcode_t insn,
904 struct arch_specific_insn *asi)
906 insn &= 0xfff0f0f0; /* Rd = r0, Rs = r0 */
907 insn |= 0x00000001; /* Rm = r1 */
909 asi->insn_handler = emulate_rd16rs8rm0_rwflags;
913 static enum kprobe_insn __kprobes
914 prep_emulate_rd16rn12rs8rm0_wflags(kprobe_opcode_t insn,
915 struct arch_specific_insn *asi)
917 insn &= 0xfff000f0; /* Rd = r0, Rn = r0 */
918 insn |= 0x00000102; /* Rs = r1, Rm = r2 */
920 asi->insn_handler = emulate_rd16rn12rs8rm0_rwflags;
924 static enum kprobe_insn __kprobes
925 prep_emulate_rdhi16rdlo12rs8rm0_wflags(kprobe_opcode_t insn,
926 struct arch_specific_insn *asi)
928 insn &= 0xfff000f0; /* RdHi = r0, RdLo = r1 */
929 insn |= 0x00001203; /* Rs = r2, Rm = r3 */
931 asi->insn_handler = emulate_rdhi16rdlo12rs8rm0_rwflags;
936 * For the instruction masking and comparisons in all the "space_*"
937 * functions below, Do _not_ rearrange the order of tests unless
938 * you're very, very sure of what you are doing. For the sake of
939 * efficiency, the masks for some tests sometimes assume other test
940 * have been done prior to them so the number of patterns to test
941 * for an instruction set can be as broad as possible to reduce the
942 * number of tests needed.
945 static enum kprobe_insn __kprobes
946 space_1111(kprobe_opcode_t insn, struct arch_specific_insn *asi)
948 /* CPS mmod == 1 : 1111 0001 0000 xx10 xxxx xxxx xx0x xxxx */
949 /* RFE : 1111 100x x0x1 xxxx xxxx 1010 xxxx xxxx */
950 /* SRS : 1111 100x x1x0 1101 xxxx 0101 xxxx xxxx */
951 if ((insn & 0xfff30020) == 0xf1020000 ||
952 (insn & 0xfe500f00) == 0xf8100a00 ||
953 (insn & 0xfe5f0f00) == 0xf84d0500)
954 return INSN_REJECTED;
956 /* PLD : 1111 01x1 x101 xxxx xxxx xxxx xxxx xxxx : */
957 if ((insn & 0xfd700000) == 0xf4500000) {
958 insn &= 0xfff0ffff; /* Rn = r0 */
960 asi->insn_handler = emulate_rn16;
964 /* BLX(1) : 1111 101x xxxx xxxx xxxx xxxx xxxx xxxx : */
965 if ((insn & 0xfe000000) == 0xfa000000) {
966 asi->insn_handler = simulate_blx1;
967 return INSN_GOOD_NO_SLOT;
970 /* SETEND : 1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
971 /* CDP2 : 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
972 if ((insn & 0xffff00f0) == 0xf1010000 ||
973 (insn & 0xff000010) == 0xfe000000) {
975 asi->insn_handler = emulate_none;
979 /* MCRR2 : 1111 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
980 /* MRRC2 : 1111 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd != Rn) */
981 if ((insn & 0xffe00000) == 0xfc400000) {
982 insn &= 0xfff00fff; /* Rn = r0 */
983 insn |= 0x00001000; /* Rd = r1 */
986 (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
990 /* LDC2 : 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
991 /* STC2 : 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
992 if ((insn & 0xfe000000) == 0xfc000000) {
993 insn &= 0xfff0ffff; /* Rn = r0 */
995 asi->insn_handler = emulate_ldcstc;
999 /* MCR2 : 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1000 /* MRC2 : 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1001 insn &= 0xffff0fff; /* Rd = r0 */
1002 asi->insn[0] = insn;
1003 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1007 static enum kprobe_insn __kprobes
1008 space_cccc_000x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1010 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx xxx0 xxxx */
1011 if ((insn & 0x0f900010) == 0x01000000) {
1013 /* BXJ : cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
1014 /* MSR : cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
1015 if ((insn & 0x0ff000f0) == 0x01200020 ||
1016 (insn & 0x0fb000f0) == 0x01200000)
1017 return INSN_REJECTED;
1019 /* MRS : cccc 0001 0x00 xxxx xxxx xxxx 0000 xxxx */
1020 if ((insn & 0x0fb00010) == 0x01000000)
1021 return prep_emulate_rd12(insn, asi);
1023 /* SMLALxy : cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
1024 if ((insn & 0x0ff00090) == 0x01400080)
1025 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1027 /* SMULWy : cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
1028 /* SMULxy : cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
1029 if ((insn & 0x0ff000b0) == 0x012000a0 ||
1030 (insn & 0x0ff00090) == 0x01600080)
1031 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1033 /* SMLAxy : cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx : Q */
1034 /* SMLAWy : cccc 0001 0010 xxxx xxxx xxxx 0x00 xxxx : Q */
1035 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1039 /* cccc 0001 0xx0 xxxx xxxx xxxx xxxx 0xx1 xxxx */
1040 else if ((insn & 0x0f900090) == 0x01000010) {
1042 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1043 if ((insn & 0xfff000f0) == 0xe1200070)
1044 return INSN_REJECTED;
1046 /* BLX(2) : cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
1047 /* BX : cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
1048 if ((insn & 0x0ff000d0) == 0x01200010) {
1049 asi->insn[0] = truecc_insn(insn);
1050 asi->insn_handler = simulate_blx2bx;
1054 /* CLZ : cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
1055 if ((insn & 0x0ff000f0) == 0x01600010)
1056 return prep_emulate_rd12rm0(insn, asi);
1058 /* QADD : cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx :Q */
1059 /* QSUB : cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx :Q */
1060 /* QDADD : cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx :Q */
1061 /* QDSUB : cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx :Q */
1062 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1065 /* cccc 0000 xxxx xxxx xxxx xxxx xxxx 1001 xxxx */
1066 else if ((insn & 0x0f000090) == 0x00000090) {
1068 /* MUL : cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx : */
1069 /* MULS : cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx :cc */
1070 /* MLA : cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx : */
1071 /* MLAS : cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx :cc */
1072 /* UMAAL : cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx : */
1073 /* UMULL : cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx : */
1074 /* UMULLS : cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx :cc */
1075 /* UMLAL : cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx : */
1076 /* UMLALS : cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx :cc */
1077 /* SMULL : cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx : */
1078 /* SMULLS : cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx :cc */
1079 /* SMLAL : cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx : */
1080 /* SMLALS : cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx :cc */
1081 if ((insn & 0x0fe000f0) == 0x00000090) {
1082 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1083 } else if ((insn & 0x0fe000f0) == 0x00200090) {
1084 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1086 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1090 /* cccc 000x xxxx xxxx xxxx xxxx xxxx 1xx1 xxxx */
1091 else if ((insn & 0x0e000090) == 0x00000090) {
1093 /* SWP : cccc 0001 0000 xxxx xxxx xxxx 1001 xxxx */
1094 /* SWPB : cccc 0001 0100 xxxx xxxx xxxx 1001 xxxx */
1095 /* LDRD : cccc 000x xxx0 xxxx xxxx xxxx 1101 xxxx */
1096 /* STRD : cccc 000x xxx0 xxxx xxxx xxxx 1111 xxxx */
1097 /* STREX : cccc 0001 1000 xxxx xxxx xxxx 1001 xxxx */
1098 /* LDREX : cccc 0001 1001 xxxx xxxx xxxx 1001 xxxx */
1099 /* LDRH : cccc 000x xxx1 xxxx xxxx xxxx 1011 xxxx */
1100 /* STRH : cccc 000x xxx0 xxxx xxxx xxxx 1011 xxxx */
1101 /* LDRSB : cccc 000x xxx1 xxxx xxxx xxxx 1101 xxxx */
1102 /* LDRSH : cccc 000x xxx1 xxxx xxxx xxxx 1111 xxxx */
1103 if ((insn & 0x0fb000f0) == 0x01000090) {
1105 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1106 } else if ((insn & 0x0e1000d0) == 0x00000d0) {
1109 insn |= 0x00002000; /* Rn = r0, Rd = r2 */
1110 if (insn & (1 << 22)) {
1113 insn |= 1; /* Rm = r1 */
1115 asi->insn[0] = insn;
1117 (insn & (1 << 5)) ? emulate_strd : emulate_ldrd;
1121 return prep_emulate_ldr_str(insn, asi);
1124 /* cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx */
1127 * ALU op with S bit and Rd == 15 :
1128 * cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx
1130 if ((insn & 0x0e10f000) == 0x0010f000)
1131 return INSN_REJECTED;
1134 * "mov ip, sp" is the most common kprobe'd instruction by far.
1135 * Check and optimize for it explicitly.
1137 if (insn == 0xe1a0c00d) {
1138 asi->insn_handler = simulate_mov_ipsp;
1139 return INSN_GOOD_NO_SLOT;
1143 * Data processing: Immediate-shift / Register-shift
1144 * ALU op : cccc 000x xxxx xxxx xxxx xxxx xxxx xxxx
1145 * CPY : cccc 0001 1010 xxxx xxxx 0000 0000 xxxx
1146 * MOV : cccc 0001 101x xxxx xxxx xxxx xxxx xxxx
1147 * *S (bit 20) updates condition codes
1148 * ADC/SBC/RSC reads the C flag
1150 insn &= 0xfff00ff0; /* Rn = r0, Rd = r0 */
1151 insn |= 0x00000001; /* Rm = r1 */
1153 insn &= 0xfffff0ff; /* register shift */
1154 insn |= 0x00000200; /* Rs = r2 */
1156 asi->insn[0] = insn;
1157 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1158 emulate_alu_rwflags : emulate_alu_rflags;
1162 static enum kprobe_insn __kprobes
1163 space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1166 * MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
1167 * Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
1168 * ALU op with S bit and Rd == 15 :
1169 * cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
1171 if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
1172 (insn & 0x0ff00000) == 0x03400000 || /* Undef */
1173 (insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
1174 return INSN_REJECTED;
1177 * Data processing: 32-bit Immediate
1178 * ALU op : cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
1179 * MOV : cccc 0011 101x xxxx xxxx xxxx xxxx xxxx
1180 * *S (bit 20) updates condition codes
1181 * ADC/SBC/RSC reads the C flag
1183 insn &= 0xffff0fff; /* Rd = r0 */
1184 asi->insn[0] = insn;
1185 asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
1186 emulate_alu_imm_rwflags : emulate_alu_imm_rflags;
1190 static enum kprobe_insn __kprobes
1191 space_cccc_0110__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1193 /* SEL : cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx GE: !!! */
1194 if ((insn & 0x0ff000f0) == 0x068000b0) {
1195 insn &= 0xfff00ff0; /* Rd = r0, Rn = r0 */
1196 insn |= 0x00000001; /* Rm = r1 */
1197 asi->insn[0] = insn;
1198 asi->insn_handler = emulate_sel;
1202 /* SSAT : cccc 0110 101x xxxx xxxx xxxx xx01 xxxx :Q */
1203 /* USAT : cccc 0110 111x xxxx xxxx xxxx xx01 xxxx :Q */
1204 /* SSAT16 : cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx :Q */
1205 /* USAT16 : cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx :Q */
1206 if ((insn & 0x0fa00030) == 0x06a00010 ||
1207 (insn & 0x0fb000f0) == 0x06a00030) {
1208 insn &= 0xffff0ff0; /* Rd = r0, Rm = r0 */
1209 asi->insn[0] = insn;
1210 asi->insn_handler = emulate_sat;
1214 /* REV : cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
1215 /* REV16 : cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
1216 /* REVSH : cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
1217 if ((insn & 0x0ff00070) == 0x06b00030 ||
1218 (insn & 0x0ff000f0) == 0x06f000b0)
1219 return prep_emulate_rd12rm0(insn, asi);
1221 /* SADD16 : cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx :GE */
1222 /* SADDSUBX : cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx :GE */
1223 /* SSUBADDX : cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx :GE */
1224 /* SSUB16 : cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx :GE */
1225 /* SADD8 : cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx :GE */
1226 /* SSUB8 : cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx :GE */
1227 /* QADD16 : cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx : */
1228 /* QADDSUBX : cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx : */
1229 /* QSUBADDX : cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx : */
1230 /* QSUB16 : cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx : */
1231 /* QADD8 : cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx : */
1232 /* QSUB8 : cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx : */
1233 /* SHADD16 : cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx : */
1234 /* SHADDSUBX : cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx : */
1235 /* SHSUBADDX : cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx : */
1236 /* SHSUB16 : cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx : */
1237 /* SHADD8 : cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx : */
1238 /* SHSUB8 : cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx : */
1239 /* UADD16 : cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx :GE */
1240 /* UADDSUBX : cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx :GE */
1241 /* USUBADDX : cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx :GE */
1242 /* USUB16 : cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx :GE */
1243 /* UADD8 : cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx :GE */
1244 /* USUB8 : cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx :GE */
1245 /* UQADD16 : cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx : */
1246 /* UQADDSUBX : cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx : */
1247 /* UQSUBADDX : cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx : */
1248 /* UQSUB16 : cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx : */
1249 /* UQADD8 : cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx : */
1250 /* UQSUB8 : cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx : */
1251 /* UHADD16 : cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx : */
1252 /* UHADDSUBX : cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx : */
1253 /* UHSUBADDX : cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx : */
1254 /* UHSUB16 : cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx : */
1255 /* UHADD8 : cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx : */
1256 /* UHSUB8 : cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx : */
1257 /* PKHBT : cccc 0110 1000 xxxx xxxx xxxx x001 xxxx : */
1258 /* PKHTB : cccc 0110 1000 xxxx xxxx xxxx x101 xxxx : */
1259 /* SXTAB16 : cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx : */
1260 /* SXTB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1261 /* SXTAB : cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx : */
1262 /* SXTAH : cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx : */
1263 /* UXTAB16 : cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx : */
1264 /* UXTAB : cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx : */
1265 /* UXTAH : cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx : */
1266 return prep_emulate_rd12rn16rm0_wflags(insn, asi);
1269 static enum kprobe_insn __kprobes
1270 space_cccc_0111__1(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1272 /* Undef : cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
1273 if ((insn & 0x0ff000f0) == 0x03f000f0)
1274 return INSN_REJECTED;
1276 /* USADA8 : cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
1277 /* USAD8 : cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
1278 if ((insn & 0x0ff000f0) == 0x07800010)
1279 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1281 /* SMLALD : cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
1282 /* SMLSLD : cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
1283 if ((insn & 0x0ff00090) == 0x07400010)
1284 return prep_emulate_rdhi16rdlo12rs8rm0_wflags(insn, asi);
1286 /* SMLAD : cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx :Q */
1287 /* SMLSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx :Q */
1288 /* SMMLA : cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx : */
1289 /* SMMLS : cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx : */
1290 if ((insn & 0x0ff00090) == 0x07000010 ||
1291 (insn & 0x0ff000d0) == 0x07500010 ||
1292 (insn & 0x0ff000d0) == 0x075000d0)
1293 return prep_emulate_rd16rn12rs8rm0_wflags(insn, asi);
1295 /* SMUSD : cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx : */
1296 /* SMUAD : cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx :Q */
1297 /* SMMUL : cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx : */
1298 return prep_emulate_rd16rs8rm0_wflags(insn, asi);
1301 static enum kprobe_insn __kprobes
1302 space_cccc_01xx(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1304 /* LDR : cccc 01xx x0x1 xxxx xxxx xxxx xxxx xxxx */
1305 /* LDRB : cccc 01xx x1x1 xxxx xxxx xxxx xxxx xxxx */
1306 /* LDRBT : cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
1307 /* LDRT : cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
1308 /* STR : cccc 01xx x0x0 xxxx xxxx xxxx xxxx xxxx */
1309 /* STRB : cccc 01xx x1x0 xxxx xxxx xxxx xxxx xxxx */
1310 /* STRBT : cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
1311 /* STRT : cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
1312 return prep_emulate_ldr_str(insn, asi);
1315 static enum kprobe_insn __kprobes
1316 space_cccc_100x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1318 /* LDM(2) : cccc 100x x101 xxxx 0xxx xxxx xxxx xxxx */
1319 /* LDM(3) : cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
1320 if ((insn & 0x0e708000) == 0x85000000 ||
1321 (insn & 0x0e508000) == 0x85010000)
1322 return INSN_REJECTED;
1324 /* LDM(1) : cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
1325 /* STM(1) : cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
1326 asi->insn[0] = truecc_insn(insn);
1327 asi->insn_handler = ((insn & 0x108000) == 0x008000) ? /* STM & R15 */
1328 simulate_stm1_pc : simulate_ldm1stm1;
1332 static enum kprobe_insn __kprobes
1333 space_cccc_101x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1335 /* B : cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
1336 /* BL : cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
1337 asi->insn[0] = truecc_insn(insn);
1338 asi->insn_handler = simulate_bbl;
1342 static enum kprobe_insn __kprobes
1343 space_cccc_1100_010x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1345 /* MCRR : cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1346 /* MRRC : cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx : (Rd!=Rn) */
1348 insn |= 0x00001000; /* Rn = r0, Rd = r1 */
1349 asi->insn[0] = insn;
1350 asi->insn_handler = (insn & (1 << 20)) ? emulate_mrrc : emulate_mcrr;
1354 static enum kprobe_insn __kprobes
1355 space_cccc_110x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1357 /* LDC : cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
1358 /* STC : cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
1359 insn &= 0xfff0ffff; /* Rn = r0 */
1360 asi->insn[0] = insn;
1361 asi->insn_handler = emulate_ldcstc;
1365 static enum kprobe_insn __kprobes
1366 space_cccc_111x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1368 /* BKPT : 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
1369 /* SWI : cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
1370 if ((insn & 0xfff000f0) == 0xe1200070 ||
1371 (insn & 0x0f000000) == 0x0f000000)
1372 return INSN_REJECTED;
1374 /* CDP : cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
1375 if ((insn & 0x0f000010) == 0x0e000000) {
1376 asi->insn[0] = insn;
1377 asi->insn_handler = emulate_none;
1381 /* MCR : cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
1382 /* MRC : cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
1383 insn &= 0xffff0fff; /* Rd = r0 */
1384 asi->insn[0] = insn;
1385 asi->insn_handler = (insn & (1 << 20)) ? emulate_rd12 : emulate_ird12;
1390 * INSN_REJECTED If instruction is one not allowed to kprobe,
1391 * INSN_GOOD If instruction is supported and uses instruction slot,
1392 * INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
1394 * For instructions we don't want to kprobe (INSN_REJECTED return result):
1395 * These are generally ones that modify the processor state making
1396 * them "hard" to simulate such as switches processor modes or
1397 * make accesses in alternate modes. Any of these could be simulated
1398 * if the work was put into it, but low return considering they
1399 * should also be very rare.
1401 enum kprobe_insn __kprobes
1402 arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1404 asi->insn[1] = KPROBE_RETURN_INSTRUCTION;
1406 if ((insn & 0xf0000000) == 0xf0000000) {
1408 return space_1111(insn, asi);
1410 } else if ((insn & 0x0e000000) == 0x00000000) {
1412 return space_cccc_000x(insn, asi);
1414 } else if ((insn & 0x0e000000) == 0x02000000) {
1416 return space_cccc_001x(insn, asi);
1418 } else if ((insn & 0x0f000010) == 0x06000010) {
1420 return space_cccc_0110__1(insn, asi);
1422 } else if ((insn & 0x0f000010) == 0x07000010) {
1424 return space_cccc_0111__1(insn, asi);
1426 } else if ((insn & 0x0c000000) == 0x04000000) {
1428 return space_cccc_01xx(insn, asi);
1430 } else if ((insn & 0x0e000000) == 0x08000000) {
1432 return space_cccc_100x(insn, asi);
1434 } else if ((insn & 0x0e000000) == 0x0a000000) {
1436 return space_cccc_101x(insn, asi);
1438 } else if ((insn & 0x0fe00000) == 0x0c400000) {
1440 return space_cccc_1100_010x(insn, asi);
1442 } else if ((insn & 0x0e000000) == 0x0c000000) {
1444 return space_cccc_110x(insn, asi);
1448 return space_cccc_111x(insn, asi);
1451 void __init arm_kprobe_decode_init(void)
1453 find_str_pc_offset();
1458 * All ARM instructions listed below.
1460 * Instructions and their general purpose registers are given.
1461 * If a particular register may not use R15, it is prefixed with a "!".
1462 * If marked with a "*" means the value returned by reading R15
1463 * is implementation defined.
1465 * ADC/ADD/AND/BIC/CMN/CMP/EOR/MOV/MVN/ORR/RSB/RSC/SBC/SUB/TEQ
1466 * TST: Rd, Rn, Rm, !Rs
1469 * BX: Rm (R15 legal, but discouraged)
1473 * LDC/2,STC/2 immediate offset & unindex: Rn
1474 * LDC/2,STC/2 immediate pre/post-indexed: !Rn
1475 * LDM(1/3): !Rn, register_list
1476 * LDM(2): !Rn, !register_list
1477 * LDR,STR,PLD immediate offset: Rd, Rn
1478 * LDR,STR,PLD register offset: Rd, Rn, !Rm
1479 * LDR,STR,PLD scaled register offset: Rd, !Rn, !Rm
1480 * LDR,STR immediate pre/post-indexed: Rd, !Rn
1481 * LDR,STR register pre/post-indexed: Rd, !Rn, !Rm
1482 * LDR,STR scaled register pre/post-indexed: Rd, !Rn, !Rm
1483 * LDRB,STRB immediate offset: !Rd, Rn
1484 * LDRB,STRB register offset: !Rd, Rn, !Rm
1485 * LDRB,STRB scaled register offset: !Rd, !Rn, !Rm
1486 * LDRB,STRB immediate pre/post-indexed: !Rd, !Rn
1487 * LDRB,STRB register pre/post-indexed: !Rd, !Rn, !Rm
1488 * LDRB,STRB scaled register pre/post-indexed: !Rd, !Rn, !Rm
1489 * LDRT,LDRBT,STRBT immediate pre/post-indexed: !Rd, !Rn
1490 * LDRT,LDRBT,STRBT register pre/post-indexed: !Rd, !Rn, !Rm
1491 * LDRT,LDRBT,STRBT scaled register pre/post-indexed: !Rd, !Rn, !Rm
1492 * LDRH/SH/SB/D,STRH/SH/SB/D immediate offset: !Rd, Rn
1493 * LDRH/SH/SB/D,STRH/SH/SB/D register offset: !Rd, Rn, !Rm
1494 * LDRH/SH/SB/D,STRH/SH/SB/D immediate pre/post-indexed: !Rd, !Rn
1495 * LDRH/SH/SB/D,STRH/SH/SB/D register pre/post-indexed: !Rd, !Rn, !Rm
1498 * MCRR/2,MRRC/2: !Rd, !Rn
1499 * MLA: !Rd, !Rn, !Rm, !Rs
1501 * MRC/2: !Rd (if Rd==15, only changes cond codes, not the register)
1503 * MUL: !Rd, !Rm, !Rs
1504 * PKH{BT,TB}: !Rd, !Rn, !Rm
1505 * QDADD,[U]QADD/16/8/SUBX: !Rd, !Rm, !Rn
1506 * QDSUB,[U]QSUB/16/8/ADDX: !Rd, !Rm, !Rn
1507 * REV/16/SH: !Rd, !Rm
1509 * {S,U}[H]ADD{16,8,SUBX},{S,U}[H]SUB{16,8,ADDX}: !Rd, !Rn, !Rm
1510 * SEL: !Rd, !Rn, !Rm
1511 * SMLA<x><y>,SMLA{D,W<y>},SMLSD,SMML{A,S}: !Rd, !Rn, !Rm, !Rs
1512 * SMLAL<x><y>,SMLA{D,LD},SMLSLD,SMMULL,SMULW<y>: !RdHi, !RdLo, !Rm, !Rs
1513 * SMMUL,SMUAD,SMUL<x><y>,SMUSD: !Rd, !Rm, !Rs
1515 * STM(1/2): !Rn, register_list* (R15 in reg list not recommended)
1516 * STRT immediate pre/post-indexed: Rd*, !Rn
1517 * STRT register pre/post-indexed: Rd*, !Rn, !Rm
1518 * STRT scaled register pre/post-indexed: Rd*, !Rn, !Rm
1519 * STREX: !Rd, !Rn, !Rm
1520 * SWP/B: !Rd, !Rn, !Rm
1521 * {S,U}XTA{B,B16,H}: !Rd, !Rn, !Rm
1522 * {S,U}XT{B,B16,H}: !Rd, !Rm
1523 * UM{AA,LA,UL}L: !RdHi, !RdLo, !Rm, !Rs
1524 * USA{D8,A8,T,T16}: !Rd, !Rm, !Rs
1526 * May transfer control by writing R15 (possible mode changes or alternate
1527 * mode accesses marked by "*"):
1528 * ALU op (* with s-bit), B, BL, BKPT, BLX(1/2), BX, BXJ, CPS*, CPY,
1529 * LDM(1), LDM(2/3)*, LDR, MOV, RFE*, SWI*
1531 * Instructions that do not take general registers, nor transfer control:
1532 * CDP/2, SETEND, SRS*