4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
8 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
9 * 2010 (c) MontaVista Software, LLC.
11 * This code is based on the sparc64 perf event code, which is in turn based
12 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
15 #define pr_fmt(fmt) "hw perfevents: " fmt
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/uaccess.h>
25 #include <asm/cputype.h>
27 #include <asm/irq_regs.h>
29 #include <asm/stacktrace.h>
31 static struct platform_device *pmu_device;
34 * Hardware lock to serialize accesses to PMU registers. Needed for the
35 * read/modify/write sequences.
37 DEFINE_SPINLOCK(pmu_lock);
40 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
41 * another platform that supports more, we need to increase this to be the
42 * largest of all platforms.
44 * ARMv7 supports up to 32 events:
45 * cycle counter CCNT + 31 events counters CNT0..30.
46 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
48 #define ARMPMU_MAX_HWEVENTS 33
50 /* The events for a given CPU. */
51 struct cpu_hw_events {
53 * The events that are active on the CPU for the given index. Index 0
56 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
59 * A 1 bit for an index indicates that the counter is being used for
60 * an event. A 0 means that the counter can be used.
62 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
65 * A 1 bit for an index indicates that the counter is actively being
68 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
70 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
73 static const char *arm_pmu_names[] = {
74 [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
75 [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
76 [ARM_PERF_PMU_ID_V6] = "v6",
77 [ARM_PERF_PMU_ID_V6MP] = "v6mpcore",
78 [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8",
79 [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9",
83 enum arm_perf_pmu_ids id;
84 irqreturn_t (*handle_irq)(int irq_num, void *dev);
85 void (*enable)(struct hw_perf_event *evt, int idx);
86 void (*disable)(struct hw_perf_event *evt, int idx);
87 int (*event_map)(int evt);
88 u64 (*raw_event)(u64);
89 int (*get_event_idx)(struct cpu_hw_events *cpuc,
90 struct hw_perf_event *hwc);
91 u32 (*read_counter)(int idx);
92 void (*write_counter)(int idx, u32 val);
99 /* Set at runtime when we know what CPU type we are. */
100 static const struct arm_pmu *armpmu;
102 enum arm_perf_pmu_ids
103 armpmu_get_pmu_id(void)
112 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
115 armpmu_get_max_events(void)
120 max_events = armpmu->num_events;
124 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
126 #define HW_OP_UNSUPPORTED 0xFFFF
129 PERF_COUNT_HW_CACHE_##_x
131 #define CACHE_OP_UNSUPPORTED 0xFFFF
133 static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
134 [PERF_COUNT_HW_CACHE_OP_MAX]
135 [PERF_COUNT_HW_CACHE_RESULT_MAX];
138 armpmu_map_cache_event(u64 config)
140 unsigned int cache_type, cache_op, cache_result, ret;
142 cache_type = (config >> 0) & 0xff;
143 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
146 cache_op = (config >> 8) & 0xff;
147 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
150 cache_result = (config >> 16) & 0xff;
151 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
154 ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
156 if (ret == CACHE_OP_UNSUPPORTED)
163 armpmu_event_set_period(struct perf_event *event,
164 struct hw_perf_event *hwc,
167 s64 left = local64_read(&hwc->period_left);
168 s64 period = hwc->sample_period;
171 if (unlikely(left <= -period)) {
173 local64_set(&hwc->period_left, left);
174 hwc->last_period = period;
178 if (unlikely(left <= 0)) {
180 local64_set(&hwc->period_left, left);
181 hwc->last_period = period;
185 if (left > (s64)armpmu->max_period)
186 left = armpmu->max_period;
188 local64_set(&hwc->prev_count, (u64)-left);
190 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
192 perf_event_update_userpage(event);
198 armpmu_event_update(struct perf_event *event,
199 struct hw_perf_event *hwc,
203 s64 prev_raw_count, new_raw_count;
207 prev_raw_count = local64_read(&hwc->prev_count);
208 new_raw_count = armpmu->read_counter(idx);
210 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
211 new_raw_count) != prev_raw_count)
214 delta = (new_raw_count << shift) - (prev_raw_count << shift);
217 local64_add(delta, &event->count);
218 local64_sub(delta, &hwc->period_left);
220 return new_raw_count;
224 armpmu_disable(struct perf_event *event)
226 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
227 struct hw_perf_event *hwc = &event->hw;
232 clear_bit(idx, cpuc->active_mask);
233 armpmu->disable(hwc, idx);
237 armpmu_event_update(event, hwc, idx);
238 cpuc->events[idx] = NULL;
239 clear_bit(idx, cpuc->used_mask);
241 perf_event_update_userpage(event);
245 armpmu_read(struct perf_event *event)
247 struct hw_perf_event *hwc = &event->hw;
249 /* Don't read disabled counters! */
253 armpmu_event_update(event, hwc, hwc->idx);
257 armpmu_unthrottle(struct perf_event *event)
259 struct hw_perf_event *hwc = &event->hw;
262 * Set the period again. Some counters can't be stopped, so when we
263 * were throttled we simply disabled the IRQ source and the counter
264 * may have been left counting. If we don't do this step then we may
265 * get an interrupt too soon or *way* too late if the overflow has
266 * happened since disabling.
268 armpmu_event_set_period(event, hwc, hwc->idx);
269 armpmu->enable(hwc, hwc->idx);
273 armpmu_enable(struct perf_event *event)
275 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
276 struct hw_perf_event *hwc = &event->hw;
280 perf_pmu_disable(event->pmu);
282 /* If we don't have a space for the counter then finish early. */
283 idx = armpmu->get_event_idx(cpuc, hwc);
290 * If there is an event in the counter we are going to use then make
291 * sure it is disabled.
294 armpmu->disable(hwc, idx);
295 cpuc->events[idx] = event;
296 set_bit(idx, cpuc->active_mask);
298 /* Set the period for the event. */
299 armpmu_event_set_period(event, hwc, idx);
301 /* Enable the event. */
302 armpmu->enable(hwc, idx);
304 /* Propagate our changes to the userspace mapping. */
305 perf_event_update_userpage(event);
308 perf_pmu_enable(event->pmu);
312 static struct pmu pmu;
315 validate_event(struct cpu_hw_events *cpuc,
316 struct perf_event *event)
318 struct hw_perf_event fake_event = event->hw;
320 if (event->pmu && event->pmu != &pmu)
323 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
327 validate_group(struct perf_event *event)
329 struct perf_event *sibling, *leader = event->group_leader;
330 struct cpu_hw_events fake_pmu;
332 memset(&fake_pmu, 0, sizeof(fake_pmu));
334 if (!validate_event(&fake_pmu, leader))
337 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
338 if (!validate_event(&fake_pmu, sibling))
342 if (!validate_event(&fake_pmu, event))
349 armpmu_reserve_hardware(void)
351 int i, err = -ENODEV, irq;
353 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
354 if (IS_ERR(pmu_device)) {
355 pr_warning("unable to reserve pmu\n");
356 return PTR_ERR(pmu_device);
359 init_pmu(ARM_PMU_DEVICE_CPU);
361 if (pmu_device->num_resources < 1) {
362 pr_err("no irqs for PMUs defined\n");
366 for (i = 0; i < pmu_device->num_resources; ++i) {
367 irq = platform_get_irq(pmu_device, i);
371 err = request_irq(irq, armpmu->handle_irq,
372 IRQF_DISABLED | IRQF_NOBALANCING,
375 pr_warning("unable to request IRQ%d for ARM perf "
382 for (i = i - 1; i >= 0; --i) {
383 irq = platform_get_irq(pmu_device, i);
387 release_pmu(pmu_device);
395 armpmu_release_hardware(void)
399 for (i = pmu_device->num_resources - 1; i >= 0; --i) {
400 irq = platform_get_irq(pmu_device, i);
406 release_pmu(pmu_device);
410 static atomic_t active_events = ATOMIC_INIT(0);
411 static DEFINE_MUTEX(pmu_reserve_mutex);
414 hw_perf_event_destroy(struct perf_event *event)
416 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
417 armpmu_release_hardware();
418 mutex_unlock(&pmu_reserve_mutex);
423 __hw_perf_event_init(struct perf_event *event)
425 struct hw_perf_event *hwc = &event->hw;
428 /* Decode the generic type into an ARM event identifier. */
429 if (PERF_TYPE_HARDWARE == event->attr.type) {
430 mapping = armpmu->event_map(event->attr.config);
431 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
432 mapping = armpmu_map_cache_event(event->attr.config);
433 } else if (PERF_TYPE_RAW == event->attr.type) {
434 mapping = armpmu->raw_event(event->attr.config);
436 pr_debug("event type %x not supported\n", event->attr.type);
441 pr_debug("event %x:%llx not supported\n", event->attr.type,
447 * Check whether we need to exclude the counter from certain modes.
448 * The ARM performance counters are on all of the time so if someone
449 * has asked us for some excludes then we have to fail.
451 if (event->attr.exclude_kernel || event->attr.exclude_user ||
452 event->attr.exclude_hv || event->attr.exclude_idle) {
453 pr_debug("ARM performance counters do not support "
459 * We don't assign an index until we actually place the event onto
460 * hardware. Use -1 to signify that we haven't decided where to put it
461 * yet. For SMP systems, each core has it's own PMU so we can't do any
462 * clever allocation or constraints checking at this point.
467 * Store the event encoding into the config_base field. config and
468 * event_base are unused as the only 2 things we need to know are
469 * the event mapping and the counter to use. The counter to use is
470 * also the indx and the config_base is the event type.
472 hwc->config_base = (unsigned long)mapping;
476 if (!hwc->sample_period) {
477 hwc->sample_period = armpmu->max_period;
478 hwc->last_period = hwc->sample_period;
479 local64_set(&hwc->period_left, hwc->sample_period);
483 if (event->group_leader != event) {
484 err = validate_group(event);
492 static int armpmu_event_init(struct perf_event *event)
496 switch (event->attr.type) {
498 case PERF_TYPE_HARDWARE:
499 case PERF_TYPE_HW_CACHE:
509 event->destroy = hw_perf_event_destroy;
511 if (!atomic_inc_not_zero(&active_events)) {
512 if (atomic_read(&active_events) > perf_max_events) {
513 atomic_dec(&active_events);
517 mutex_lock(&pmu_reserve_mutex);
518 if (atomic_read(&active_events) == 0) {
519 err = armpmu_reserve_hardware();
523 atomic_inc(&active_events);
524 mutex_unlock(&pmu_reserve_mutex);
530 err = __hw_perf_event_init(event);
532 hw_perf_event_destroy(event);
537 static void armpmu_pmu_enable(struct pmu *pmu)
539 /* Enable all of the perf events on hardware. */
541 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
546 for (idx = 0; idx <= armpmu->num_events; ++idx) {
547 struct perf_event *event = cpuc->events[idx];
552 armpmu->enable(&event->hw, idx);
558 static void armpmu_pmu_disable(struct pmu *pmu)
564 static struct pmu pmu = {
565 .pmu_enable = armpmu_pmu_enable,
566 .pmu_disable= armpmu_pmu_disable,
567 .event_init = armpmu_event_init,
568 .enable = armpmu_enable,
569 .disable = armpmu_disable,
570 .unthrottle = armpmu_unthrottle,
575 * ARMv6 Performance counter handling code.
577 * ARMv6 has 2 configurable performance counters and a single cycle counter.
578 * They all share a single reset bit but can be written to zero so we can use
581 * The counters can't be individually enabled or disabled so when we remove
582 * one event and replace it with another we could get spurious counts from the
583 * wrong event. However, we can take advantage of the fact that the
584 * performance counters can export events to the event bus, and the event bus
585 * itself can be monitored. This requires that we *don't* export the events to
586 * the event bus. The procedure for disabling a configurable counter is:
587 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
588 * effectively stops the counter from counting.
589 * - disable the counter's interrupt generation (each counter has it's
590 * own interrupt enable bit).
591 * Once stopped, the counter value can be written as 0 to reset.
593 * To enable a counter:
594 * - enable the counter's interrupt generation.
595 * - set the new event type.
597 * Note: the dedicated cycle counter only counts cycles and can't be
598 * enabled/disabled independently of the others. When we want to disable the
599 * cycle counter, we have to just disable the interrupt reporting and start
600 * ignoring that counter. When re-enabling, we have to reset the value and
601 * enable the interrupt.
604 enum armv6_perf_types {
605 ARMV6_PERFCTR_ICACHE_MISS = 0x0,
606 ARMV6_PERFCTR_IBUF_STALL = 0x1,
607 ARMV6_PERFCTR_DDEP_STALL = 0x2,
608 ARMV6_PERFCTR_ITLB_MISS = 0x3,
609 ARMV6_PERFCTR_DTLB_MISS = 0x4,
610 ARMV6_PERFCTR_BR_EXEC = 0x5,
611 ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
612 ARMV6_PERFCTR_INSTR_EXEC = 0x7,
613 ARMV6_PERFCTR_DCACHE_HIT = 0x9,
614 ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
615 ARMV6_PERFCTR_DCACHE_MISS = 0xB,
616 ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
617 ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
618 ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
619 ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
620 ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
621 ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
622 ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
623 ARMV6_PERFCTR_NOP = 0x20,
626 enum armv6_counters {
627 ARMV6_CYCLE_COUNTER = 1,
633 * The hardware events that we support. We do support cache operations but
634 * we have harvard caches and no way to combine instruction and data
635 * accesses/misses in hardware.
637 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
638 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
639 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
640 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
641 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
642 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
643 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
644 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
647 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
648 [PERF_COUNT_HW_CACHE_OP_MAX]
649 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
652 * The performance counters don't differentiate between read
653 * and write accesses/misses so this isn't strictly correct,
654 * but it's the best we can do. Writes and reads get
658 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
659 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
662 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
663 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
666 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
667 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
672 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
673 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
676 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
677 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
680 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
681 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
686 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
687 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
690 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
691 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
694 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
695 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
700 * The ARM performance counters can count micro DTLB misses,
701 * micro ITLB misses and main TLB misses. There isn't an event
702 * for TLB misses, so use the micro misses here and if users
703 * want the main TLB misses they can use a raw counter.
706 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
707 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
710 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
711 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
714 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
715 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
720 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
721 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
724 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
725 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
728 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
729 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
734 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
735 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
738 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
739 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
742 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
743 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
748 enum armv6mpcore_perf_types {
749 ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
750 ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
751 ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
752 ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
753 ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
754 ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
755 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
756 ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
757 ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
758 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
759 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
760 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
761 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
762 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
763 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
764 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
765 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
766 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
767 ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
768 ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
772 * The hardware events that we support. We do support cache operations but
773 * we have harvard caches and no way to combine instruction and data
774 * accesses/misses in hardware.
776 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
777 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
778 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
779 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
780 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
781 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
782 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
783 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
786 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
787 [PERF_COUNT_HW_CACHE_OP_MAX]
788 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
792 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
794 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
798 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
800 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
803 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
804 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
809 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
810 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
813 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
814 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
817 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
818 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
823 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
824 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
827 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
828 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
831 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
832 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
837 * The ARM performance counters can count micro DTLB misses,
838 * micro ITLB misses and main TLB misses. There isn't an event
839 * for TLB misses, so use the micro misses here and if users
840 * want the main TLB misses they can use a raw counter.
843 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
844 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
847 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
848 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
851 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
852 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
857 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
858 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
861 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
862 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
865 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
866 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
871 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
872 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
875 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
876 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
879 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
880 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
885 static inline unsigned long
886 armv6_pmcr_read(void)
889 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
894 armv6_pmcr_write(unsigned long val)
896 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
899 #define ARMV6_PMCR_ENABLE (1 << 0)
900 #define ARMV6_PMCR_CTR01_RESET (1 << 1)
901 #define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
902 #define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
903 #define ARMV6_PMCR_COUNT0_IEN (1 << 4)
904 #define ARMV6_PMCR_COUNT1_IEN (1 << 5)
905 #define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
906 #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
907 #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
908 #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
909 #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
910 #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
911 #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
912 #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
914 #define ARMV6_PMCR_OVERFLOWED_MASK \
915 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
916 ARMV6_PMCR_CCOUNT_OVERFLOW)
919 armv6_pmcr_has_overflowed(unsigned long pmcr)
921 return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
925 armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
926 enum armv6_counters counter)
930 if (ARMV6_CYCLE_COUNTER == counter)
931 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
932 else if (ARMV6_COUNTER0 == counter)
933 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
934 else if (ARMV6_COUNTER1 == counter)
935 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
937 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
943 armv6pmu_read_counter(int counter)
945 unsigned long value = 0;
947 if (ARMV6_CYCLE_COUNTER == counter)
948 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
949 else if (ARMV6_COUNTER0 == counter)
950 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
951 else if (ARMV6_COUNTER1 == counter)
952 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
954 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
960 armv6pmu_write_counter(int counter,
963 if (ARMV6_CYCLE_COUNTER == counter)
964 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
965 else if (ARMV6_COUNTER0 == counter)
966 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
967 else if (ARMV6_COUNTER1 == counter)
968 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
970 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
974 armv6pmu_enable_event(struct hw_perf_event *hwc,
977 unsigned long val, mask, evt, flags;
979 if (ARMV6_CYCLE_COUNTER == idx) {
981 evt = ARMV6_PMCR_CCOUNT_IEN;
982 } else if (ARMV6_COUNTER0 == idx) {
983 mask = ARMV6_PMCR_EVT_COUNT0_MASK;
984 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
985 ARMV6_PMCR_COUNT0_IEN;
986 } else if (ARMV6_COUNTER1 == idx) {
987 mask = ARMV6_PMCR_EVT_COUNT1_MASK;
988 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
989 ARMV6_PMCR_COUNT1_IEN;
991 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
996 * Mask out the current event and set the counter to count the event
997 * that we're interested in.
999 spin_lock_irqsave(&pmu_lock, flags);
1000 val = armv6_pmcr_read();
1003 armv6_pmcr_write(val);
1004 spin_unlock_irqrestore(&pmu_lock, flags);
1008 armv6pmu_handle_irq(int irq_num,
1011 unsigned long pmcr = armv6_pmcr_read();
1012 struct perf_sample_data data;
1013 struct cpu_hw_events *cpuc;
1014 struct pt_regs *regs;
1017 if (!armv6_pmcr_has_overflowed(pmcr))
1020 regs = get_irq_regs();
1023 * The interrupts are cleared by writing the overflow flags back to
1024 * the control register. All of the other bits don't have any effect
1025 * if they are rewritten, so write the whole value back.
1027 armv6_pmcr_write(pmcr);
1029 perf_sample_data_init(&data, 0);
1031 cpuc = &__get_cpu_var(cpu_hw_events);
1032 for (idx = 0; idx <= armpmu->num_events; ++idx) {
1033 struct perf_event *event = cpuc->events[idx];
1034 struct hw_perf_event *hwc;
1036 if (!test_bit(idx, cpuc->active_mask))
1040 * We have a single interrupt for all counters. Check that
1041 * each counter has overflowed before we process it.
1043 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
1047 armpmu_event_update(event, hwc, idx);
1048 data.period = event->hw.last_period;
1049 if (!armpmu_event_set_period(event, hwc, idx))
1052 if (perf_event_overflow(event, 0, &data, regs))
1053 armpmu->disable(hwc, idx);
1057 * Handle the pending perf events.
1059 * Note: this call *must* be run with interrupts enabled. For
1060 * platforms that can have the PMU interrupts raised as a PMI, this
1063 perf_event_do_pending();
1069 armv6pmu_start(void)
1071 unsigned long flags, val;
1073 spin_lock_irqsave(&pmu_lock, flags);
1074 val = armv6_pmcr_read();
1075 val |= ARMV6_PMCR_ENABLE;
1076 armv6_pmcr_write(val);
1077 spin_unlock_irqrestore(&pmu_lock, flags);
1083 unsigned long flags, val;
1085 spin_lock_irqsave(&pmu_lock, flags);
1086 val = armv6_pmcr_read();
1087 val &= ~ARMV6_PMCR_ENABLE;
1088 armv6_pmcr_write(val);
1089 spin_unlock_irqrestore(&pmu_lock, flags);
1093 armv6pmu_event_map(int config)
1095 int mapping = armv6_perf_map[config];
1096 if (HW_OP_UNSUPPORTED == mapping)
1097 mapping = -EOPNOTSUPP;
1102 armv6mpcore_pmu_event_map(int config)
1104 int mapping = armv6mpcore_perf_map[config];
1105 if (HW_OP_UNSUPPORTED == mapping)
1106 mapping = -EOPNOTSUPP;
1111 armv6pmu_raw_event(u64 config)
1113 return config & 0xff;
1117 armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
1118 struct hw_perf_event *event)
1120 /* Always place a cycle counter into the cycle counter. */
1121 if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
1122 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
1125 return ARMV6_CYCLE_COUNTER;
1128 * For anything other than a cycle counter, try and use
1129 * counter0 and counter1.
1131 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
1132 return ARMV6_COUNTER1;
1135 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
1136 return ARMV6_COUNTER0;
1139 /* The counters are all in use. */
1145 armv6pmu_disable_event(struct hw_perf_event *hwc,
1148 unsigned long val, mask, evt, flags;
1150 if (ARMV6_CYCLE_COUNTER == idx) {
1151 mask = ARMV6_PMCR_CCOUNT_IEN;
1153 } else if (ARMV6_COUNTER0 == idx) {
1154 mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
1155 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
1156 } else if (ARMV6_COUNTER1 == idx) {
1157 mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
1158 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
1160 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1165 * Mask out the current event and set the counter to count the number
1166 * of ETM bus signal assertion cycles. The external reporting should
1167 * be disabled and so this should never increment.
1169 spin_lock_irqsave(&pmu_lock, flags);
1170 val = armv6_pmcr_read();
1173 armv6_pmcr_write(val);
1174 spin_unlock_irqrestore(&pmu_lock, flags);
1178 armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
1181 unsigned long val, mask, flags, evt = 0;
1183 if (ARMV6_CYCLE_COUNTER == idx) {
1184 mask = ARMV6_PMCR_CCOUNT_IEN;
1185 } else if (ARMV6_COUNTER0 == idx) {
1186 mask = ARMV6_PMCR_COUNT0_IEN;
1187 } else if (ARMV6_COUNTER1 == idx) {
1188 mask = ARMV6_PMCR_COUNT1_IEN;
1190 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1195 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
1196 * simply disable the interrupt reporting.
1198 spin_lock_irqsave(&pmu_lock, flags);
1199 val = armv6_pmcr_read();
1202 armv6_pmcr_write(val);
1203 spin_unlock_irqrestore(&pmu_lock, flags);
1206 static const struct arm_pmu armv6pmu = {
1207 .id = ARM_PERF_PMU_ID_V6,
1208 .handle_irq = armv6pmu_handle_irq,
1209 .enable = armv6pmu_enable_event,
1210 .disable = armv6pmu_disable_event,
1211 .event_map = armv6pmu_event_map,
1212 .raw_event = armv6pmu_raw_event,
1213 .read_counter = armv6pmu_read_counter,
1214 .write_counter = armv6pmu_write_counter,
1215 .get_event_idx = armv6pmu_get_event_idx,
1216 .start = armv6pmu_start,
1217 .stop = armv6pmu_stop,
1219 .max_period = (1LLU << 32) - 1,
1223 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
1224 * that some of the events have different enumerations and that there is no
1225 * *hack* to stop the programmable counters. To stop the counters we simply
1226 * disable the interrupt reporting and update the event. When unthrottling we
1227 * reset the period and enable the interrupt reporting.
1229 static const struct arm_pmu armv6mpcore_pmu = {
1230 .id = ARM_PERF_PMU_ID_V6MP,
1231 .handle_irq = armv6pmu_handle_irq,
1232 .enable = armv6pmu_enable_event,
1233 .disable = armv6mpcore_pmu_disable_event,
1234 .event_map = armv6mpcore_pmu_event_map,
1235 .raw_event = armv6pmu_raw_event,
1236 .read_counter = armv6pmu_read_counter,
1237 .write_counter = armv6pmu_write_counter,
1238 .get_event_idx = armv6pmu_get_event_idx,
1239 .start = armv6pmu_start,
1240 .stop = armv6pmu_stop,
1242 .max_period = (1LLU << 32) - 1,
1246 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
1248 * Copied from ARMv6 code, with the low level code inspired
1249 * by the ARMv7 Oprofile code.
1251 * Cortex-A8 has up to 4 configurable performance counters and
1252 * a single cycle counter.
1253 * Cortex-A9 has up to 31 configurable performance counters and
1254 * a single cycle counter.
1256 * All counters can be enabled/disabled and IRQ masked separately. The cycle
1257 * counter and all 4 performance counters together can be reset separately.
1260 /* Common ARMv7 event types */
1261 enum armv7_perf_types {
1262 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
1263 ARMV7_PERFCTR_IFETCH_MISS = 0x01,
1264 ARMV7_PERFCTR_ITLB_MISS = 0x02,
1265 ARMV7_PERFCTR_DCACHE_REFILL = 0x03,
1266 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04,
1267 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
1268 ARMV7_PERFCTR_DREAD = 0x06,
1269 ARMV7_PERFCTR_DWRITE = 0x07,
1271 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
1272 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
1273 ARMV7_PERFCTR_CID_WRITE = 0x0B,
1274 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
1276 * - all branch instructions,
1277 * - instructions that explicitly write the PC,
1278 * - exception generating instructions.
1280 ARMV7_PERFCTR_PC_WRITE = 0x0C,
1281 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
1282 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F,
1283 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
1284 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
1286 ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12,
1288 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
1291 /* ARMv7 Cortex-A8 specific event types */
1292 enum armv7_a8_perf_types {
1293 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
1295 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
1297 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40,
1298 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41,
1299 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42,
1300 ARMV7_PERFCTR_L2_ACCESS = 0x43,
1301 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
1302 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
1303 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
1304 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
1305 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
1306 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
1307 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
1308 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
1309 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
1310 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
1311 ARMV7_PERFCTR_L2_NEON = 0x4E,
1312 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
1313 ARMV7_PERFCTR_L1_INST = 0x50,
1314 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
1315 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
1316 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
1317 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
1318 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
1319 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
1320 ARMV7_PERFCTR_CYCLES_INST = 0x57,
1321 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
1322 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
1323 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
1325 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
1326 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
1327 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
1330 /* ARMv7 Cortex-A9 specific event types */
1331 enum armv7_a9_perf_types {
1332 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40,
1333 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
1334 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
1336 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
1337 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
1339 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
1340 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
1341 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
1342 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
1343 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
1344 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
1345 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
1346 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
1347 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
1349 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
1351 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
1352 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
1353 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
1354 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
1355 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
1357 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
1358 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
1359 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
1360 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
1361 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
1362 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
1363 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
1365 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
1366 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
1368 ARMV7_PERFCTR_ISB_INST = 0x90,
1369 ARMV7_PERFCTR_DSB_INST = 0x91,
1370 ARMV7_PERFCTR_DMB_INST = 0x92,
1371 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
1373 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
1374 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
1375 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
1376 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
1377 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
1378 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
1382 * Cortex-A8 HW events mapping
1384 * The hardware events that we support. We do support cache operations but
1385 * we have harvard caches and no way to combine instruction and data
1386 * accesses/misses in hardware.
1388 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
1389 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1390 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
1391 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
1392 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
1393 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1394 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1395 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1398 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1399 [PERF_COUNT_HW_CACHE_OP_MAX]
1400 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1403 * The performance counters don't differentiate between read
1404 * and write accesses/misses so this isn't strictly correct,
1405 * but it's the best we can do. Writes and reads get
1409 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1410 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1413 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1414 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1416 [C(OP_PREFETCH)] = {
1417 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1418 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1423 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1424 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1427 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1428 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1430 [C(OP_PREFETCH)] = {
1431 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1432 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1437 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1438 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1441 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1442 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1444 [C(OP_PREFETCH)] = {
1445 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1446 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1451 * Only ITLB misses and DTLB refills are supported.
1452 * If users want the DTLB refills misses a raw counter
1456 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1457 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1460 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1461 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1463 [C(OP_PREFETCH)] = {
1464 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1465 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1470 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1471 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1474 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1475 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1477 [C(OP_PREFETCH)] = {
1478 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1479 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1484 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1486 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1489 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1491 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1493 [C(OP_PREFETCH)] = {
1494 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1495 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1501 * Cortex-A9 HW events mapping
1503 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
1504 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1505 [PERF_COUNT_HW_INSTRUCTIONS] =
1506 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
1507 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
1508 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
1509 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1510 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1511 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1514 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1515 [PERF_COUNT_HW_CACHE_OP_MAX]
1516 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1519 * The performance counters don't differentiate between read
1520 * and write accesses/misses so this isn't strictly correct,
1521 * but it's the best we can do. Writes and reads get
1525 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1526 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1529 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1530 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1532 [C(OP_PREFETCH)] = {
1533 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1534 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1539 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1540 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1543 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1544 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1546 [C(OP_PREFETCH)] = {
1547 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1548 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1553 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1554 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1557 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1558 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1560 [C(OP_PREFETCH)] = {
1561 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1562 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1567 * Only ITLB misses and DTLB refills are supported.
1568 * If users want the DTLB refills misses a raw counter
1572 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1573 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1576 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1577 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1579 [C(OP_PREFETCH)] = {
1580 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1581 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1586 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1587 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1590 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1591 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1593 [C(OP_PREFETCH)] = {
1594 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1595 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1600 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1602 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1605 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1607 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1609 [C(OP_PREFETCH)] = {
1610 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1611 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1617 * Perf Events counters
1619 enum armv7_counters {
1620 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */
1621 ARMV7_COUNTER0 = 2, /* First event counter */
1625 * The cycle counter is ARMV7_CYCLE_COUNTER.
1626 * The first event counter is ARMV7_COUNTER0.
1627 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1629 #define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1)
1632 * ARMv7 low level PMNC access
1636 * Per-CPU PMNC: config reg
1638 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
1639 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
1640 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
1641 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
1642 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
1643 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
1644 #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
1645 #define ARMV7_PMNC_N_MASK 0x1f
1646 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
1649 * Available counters
1651 #define ARMV7_CNT0 0 /* First event counter */
1652 #define ARMV7_CCNT 31 /* Cycle counter */
1654 /* Perf Event to low level counters mapping */
1655 #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
1658 * CNTENS: counters enable reg
1660 #define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1661 #define ARMV7_CNTENS_C (1 << ARMV7_CCNT)
1664 * CNTENC: counters disable reg
1666 #define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1667 #define ARMV7_CNTENC_C (1 << ARMV7_CCNT)
1670 * INTENS: counters overflow interrupt enable reg
1672 #define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1673 #define ARMV7_INTENS_C (1 << ARMV7_CCNT)
1676 * INTENC: counters overflow interrupt disable reg
1678 #define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1679 #define ARMV7_INTENC_C (1 << ARMV7_CCNT)
1682 * EVTSEL: Event selection reg
1684 #define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */
1687 * SELECT: Counter selection reg
1689 #define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */
1692 * FLAG: counters overflow flag status reg
1694 #define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1695 #define ARMV7_FLAG_C (1 << ARMV7_CCNT)
1696 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
1697 #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
1699 static inline unsigned long armv7_pmnc_read(void)
1702 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
1706 static inline void armv7_pmnc_write(unsigned long val)
1708 val &= ARMV7_PMNC_MASK;
1709 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
1712 static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
1714 return pmnc & ARMV7_OVERFLOWED_MASK;
1717 static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
1718 enum armv7_counters counter)
1722 if (counter == ARMV7_CYCLE_COUNTER)
1723 ret = pmnc & ARMV7_FLAG_C;
1724 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1725 ret = pmnc & ARMV7_FLAG_P(counter);
1727 pr_err("CPU%u checking wrong counter %d overflow status\n",
1728 smp_processor_id(), counter);
1733 static inline int armv7_pmnc_select_counter(unsigned int idx)
1737 if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
1738 pr_err("CPU%u selecting wrong PMNC counter"
1739 " %d\n", smp_processor_id(), idx);
1743 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
1744 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
1749 static inline u32 armv7pmu_read_counter(int idx)
1751 unsigned long value = 0;
1753 if (idx == ARMV7_CYCLE_COUNTER)
1754 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
1755 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1756 if (armv7_pmnc_select_counter(idx) == idx)
1757 asm volatile("mrc p15, 0, %0, c9, c13, 2"
1760 pr_err("CPU%u reading wrong counter %d\n",
1761 smp_processor_id(), idx);
1766 static inline void armv7pmu_write_counter(int idx, u32 value)
1768 if (idx == ARMV7_CYCLE_COUNTER)
1769 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
1770 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1771 if (armv7_pmnc_select_counter(idx) == idx)
1772 asm volatile("mcr p15, 0, %0, c9, c13, 2"
1775 pr_err("CPU%u writing wrong counter %d\n",
1776 smp_processor_id(), idx);
1779 static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
1781 if (armv7_pmnc_select_counter(idx) == idx) {
1782 val &= ARMV7_EVTSEL_MASK;
1783 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
1787 static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
1791 if ((idx != ARMV7_CYCLE_COUNTER) &&
1792 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1793 pr_err("CPU%u enabling wrong PMNC counter"
1794 " %d\n", smp_processor_id(), idx);
1798 if (idx == ARMV7_CYCLE_COUNTER)
1799 val = ARMV7_CNTENS_C;
1801 val = ARMV7_CNTENS_P(idx);
1803 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
1808 static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
1813 if ((idx != ARMV7_CYCLE_COUNTER) &&
1814 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1815 pr_err("CPU%u disabling wrong PMNC counter"
1816 " %d\n", smp_processor_id(), idx);
1820 if (idx == ARMV7_CYCLE_COUNTER)
1821 val = ARMV7_CNTENC_C;
1823 val = ARMV7_CNTENC_P(idx);
1825 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
1830 static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
1834 if ((idx != ARMV7_CYCLE_COUNTER) &&
1835 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1836 pr_err("CPU%u enabling wrong PMNC counter"
1837 " interrupt enable %d\n", smp_processor_id(), idx);
1841 if (idx == ARMV7_CYCLE_COUNTER)
1842 val = ARMV7_INTENS_C;
1844 val = ARMV7_INTENS_P(idx);
1846 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
1851 static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
1855 if ((idx != ARMV7_CYCLE_COUNTER) &&
1856 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1857 pr_err("CPU%u disabling wrong PMNC counter"
1858 " interrupt enable %d\n", smp_processor_id(), idx);
1862 if (idx == ARMV7_CYCLE_COUNTER)
1863 val = ARMV7_INTENC_C;
1865 val = ARMV7_INTENC_P(idx);
1867 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
1872 static inline u32 armv7_pmnc_getreset_flags(void)
1877 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1879 /* Write to clear flags */
1880 val &= ARMV7_FLAG_MASK;
1881 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
1887 static void armv7_pmnc_dump_regs(void)
1892 printk(KERN_INFO "PMNC registers dump:\n");
1894 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
1895 printk(KERN_INFO "PMNC =0x%08x\n", val);
1897 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
1898 printk(KERN_INFO "CNTENS=0x%08x\n", val);
1900 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
1901 printk(KERN_INFO "INTENS=0x%08x\n", val);
1903 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1904 printk(KERN_INFO "FLAGS =0x%08x\n", val);
1906 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
1907 printk(KERN_INFO "SELECT=0x%08x\n", val);
1909 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
1910 printk(KERN_INFO "CCNT =0x%08x\n", val);
1912 for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
1913 armv7_pmnc_select_counter(cnt);
1914 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
1915 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
1916 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1917 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
1918 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
1919 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1924 void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1926 unsigned long flags;
1929 * Enable counter and interrupt, and set the counter to count
1930 * the event that we're interested in.
1932 spin_lock_irqsave(&pmu_lock, flags);
1937 armv7_pmnc_disable_counter(idx);
1940 * Set event (if destined for PMNx counters)
1941 * We don't need to set the event if it's a cycle count
1943 if (idx != ARMV7_CYCLE_COUNTER)
1944 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1947 * Enable interrupt for this counter
1949 armv7_pmnc_enable_intens(idx);
1954 armv7_pmnc_enable_counter(idx);
1956 spin_unlock_irqrestore(&pmu_lock, flags);
1959 static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1961 unsigned long flags;
1964 * Disable counter and interrupt
1966 spin_lock_irqsave(&pmu_lock, flags);
1971 armv7_pmnc_disable_counter(idx);
1974 * Disable interrupt for this counter
1976 armv7_pmnc_disable_intens(idx);
1978 spin_unlock_irqrestore(&pmu_lock, flags);
1981 static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1984 struct perf_sample_data data;
1985 struct cpu_hw_events *cpuc;
1986 struct pt_regs *regs;
1990 * Get and reset the IRQ flags
1992 pmnc = armv7_pmnc_getreset_flags();
1995 * Did an overflow occur?
1997 if (!armv7_pmnc_has_overflowed(pmnc))
2001 * Handle the counter(s) overflow(s)
2003 regs = get_irq_regs();
2005 perf_sample_data_init(&data, 0);
2007 cpuc = &__get_cpu_var(cpu_hw_events);
2008 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2009 struct perf_event *event = cpuc->events[idx];
2010 struct hw_perf_event *hwc;
2012 if (!test_bit(idx, cpuc->active_mask))
2016 * We have a single interrupt for all counters. Check that
2017 * each counter has overflowed before we process it.
2019 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
2023 armpmu_event_update(event, hwc, idx);
2024 data.period = event->hw.last_period;
2025 if (!armpmu_event_set_period(event, hwc, idx))
2028 if (perf_event_overflow(event, 0, &data, regs))
2029 armpmu->disable(hwc, idx);
2033 * Handle the pending perf events.
2035 * Note: this call *must* be run with interrupts enabled. For
2036 * platforms that can have the PMU interrupts raised as a PMI, this
2039 perf_event_do_pending();
2044 static void armv7pmu_start(void)
2046 unsigned long flags;
2048 spin_lock_irqsave(&pmu_lock, flags);
2049 /* Enable all counters */
2050 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
2051 spin_unlock_irqrestore(&pmu_lock, flags);
2054 static void armv7pmu_stop(void)
2056 unsigned long flags;
2058 spin_lock_irqsave(&pmu_lock, flags);
2059 /* Disable all counters */
2060 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
2061 spin_unlock_irqrestore(&pmu_lock, flags);
2064 static inline int armv7_a8_pmu_event_map(int config)
2066 int mapping = armv7_a8_perf_map[config];
2067 if (HW_OP_UNSUPPORTED == mapping)
2068 mapping = -EOPNOTSUPP;
2072 static inline int armv7_a9_pmu_event_map(int config)
2074 int mapping = armv7_a9_perf_map[config];
2075 if (HW_OP_UNSUPPORTED == mapping)
2076 mapping = -EOPNOTSUPP;
2080 static u64 armv7pmu_raw_event(u64 config)
2082 return config & 0xff;
2085 static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
2086 struct hw_perf_event *event)
2090 /* Always place a cycle counter into the cycle counter. */
2091 if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
2092 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
2095 return ARMV7_CYCLE_COUNTER;
2098 * For anything other than a cycle counter, try and use
2099 * the events counters
2101 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
2102 if (!test_and_set_bit(idx, cpuc->used_mask))
2106 /* The counters are all in use. */
2111 static struct arm_pmu armv7pmu = {
2112 .handle_irq = armv7pmu_handle_irq,
2113 .enable = armv7pmu_enable_event,
2114 .disable = armv7pmu_disable_event,
2115 .raw_event = armv7pmu_raw_event,
2116 .read_counter = armv7pmu_read_counter,
2117 .write_counter = armv7pmu_write_counter,
2118 .get_event_idx = armv7pmu_get_event_idx,
2119 .start = armv7pmu_start,
2120 .stop = armv7pmu_stop,
2121 .max_period = (1LLU << 32) - 1,
2124 static u32 __init armv7_reset_read_pmnc(void)
2128 /* Initialize & Reset PMNC: C and P bits */
2129 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
2131 /* Read the nb of CNTx counters supported from PMNC */
2132 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
2134 /* Add the CPU cycles counter and return */
2139 * ARMv5 [xscale] Performance counter handling code.
2141 * Based on xscale OProfile code.
2143 * There are two variants of the xscale PMU that we support:
2144 * - xscale1pmu: 2 event counters and a cycle counter
2145 * - xscale2pmu: 4 event counters and a cycle counter
2146 * The two variants share event definitions, but have different
2150 enum xscale_perf_types {
2151 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
2152 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
2153 XSCALE_PERFCTR_DATA_STALL = 0x02,
2154 XSCALE_PERFCTR_ITLB_MISS = 0x03,
2155 XSCALE_PERFCTR_DTLB_MISS = 0x04,
2156 XSCALE_PERFCTR_BRANCH = 0x05,
2157 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
2158 XSCALE_PERFCTR_INSTRUCTION = 0x07,
2159 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
2160 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
2161 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
2162 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
2163 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
2164 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
2165 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
2166 XSCALE_PERFCTR_BCU_FULL = 0x11,
2167 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
2168 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
2169 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
2170 XSCALE_PERFCTR_RMW = 0x16,
2171 /* XSCALE_PERFCTR_CCNT is not hardware defined */
2172 XSCALE_PERFCTR_CCNT = 0xFE,
2173 XSCALE_PERFCTR_UNUSED = 0xFF,
2176 enum xscale_counters {
2177 XSCALE_CYCLE_COUNTER = 1,
2184 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
2185 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
2186 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
2187 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
2188 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
2189 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
2190 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
2191 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
2194 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
2195 [PERF_COUNT_HW_CACHE_OP_MAX]
2196 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2199 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2200 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2203 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2204 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2206 [C(OP_PREFETCH)] = {
2207 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2208 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2213 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2214 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2217 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2218 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2220 [C(OP_PREFETCH)] = {
2221 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2222 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2227 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2228 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2231 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2232 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2234 [C(OP_PREFETCH)] = {
2235 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2236 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2241 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2242 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2245 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2246 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2248 [C(OP_PREFETCH)] = {
2249 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2250 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2255 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2256 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2259 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2260 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2262 [C(OP_PREFETCH)] = {
2263 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2264 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2269 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2270 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2273 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2274 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2276 [C(OP_PREFETCH)] = {
2277 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2278 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2283 #define XSCALE_PMU_ENABLE 0x001
2284 #define XSCALE_PMN_RESET 0x002
2285 #define XSCALE_CCNT_RESET 0x004
2286 #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
2287 #define XSCALE_PMU_CNT64 0x008
2290 xscalepmu_event_map(int config)
2292 int mapping = xscale_perf_map[config];
2293 if (HW_OP_UNSUPPORTED == mapping)
2294 mapping = -EOPNOTSUPP;
2299 xscalepmu_raw_event(u64 config)
2301 return config & 0xff;
2304 #define XSCALE1_OVERFLOWED_MASK 0x700
2305 #define XSCALE1_CCOUNT_OVERFLOW 0x400
2306 #define XSCALE1_COUNT0_OVERFLOW 0x100
2307 #define XSCALE1_COUNT1_OVERFLOW 0x200
2308 #define XSCALE1_CCOUNT_INT_EN 0x040
2309 #define XSCALE1_COUNT0_INT_EN 0x010
2310 #define XSCALE1_COUNT1_INT_EN 0x020
2311 #define XSCALE1_COUNT0_EVT_SHFT 12
2312 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
2313 #define XSCALE1_COUNT1_EVT_SHFT 20
2314 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
2317 xscale1pmu_read_pmnc(void)
2320 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
2325 xscale1pmu_write_pmnc(u32 val)
2327 /* upper 4bits and 7, 11 are write-as-0 */
2329 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
2333 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
2334 enum xscale_counters counter)
2339 case XSCALE_CYCLE_COUNTER:
2340 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
2342 case XSCALE_COUNTER0:
2343 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
2345 case XSCALE_COUNTER1:
2346 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
2349 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2356 xscale1pmu_handle_irq(int irq_num, void *dev)
2359 struct perf_sample_data data;
2360 struct cpu_hw_events *cpuc;
2361 struct pt_regs *regs;
2365 * NOTE: there's an A stepping erratum that states if an overflow
2366 * bit already exists and another occurs, the previous
2367 * Overflow bit gets cleared. There's no workaround.
2368 * Fixed in B stepping or later.
2370 pmnc = xscale1pmu_read_pmnc();
2373 * Write the value back to clear the overflow flags. Overflow
2374 * flags remain in pmnc for use below. We also disable the PMU
2375 * while we process the interrupt.
2377 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2379 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
2382 regs = get_irq_regs();
2384 perf_sample_data_init(&data, 0);
2386 cpuc = &__get_cpu_var(cpu_hw_events);
2387 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2388 struct perf_event *event = cpuc->events[idx];
2389 struct hw_perf_event *hwc;
2391 if (!test_bit(idx, cpuc->active_mask))
2394 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
2398 armpmu_event_update(event, hwc, idx);
2399 data.period = event->hw.last_period;
2400 if (!armpmu_event_set_period(event, hwc, idx))
2403 if (perf_event_overflow(event, 0, &data, regs))
2404 armpmu->disable(hwc, idx);
2407 perf_event_do_pending();
2410 * Re-enable the PMU.
2412 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2413 xscale1pmu_write_pmnc(pmnc);
2419 xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
2421 unsigned long val, mask, evt, flags;
2424 case XSCALE_CYCLE_COUNTER:
2426 evt = XSCALE1_CCOUNT_INT_EN;
2428 case XSCALE_COUNTER0:
2429 mask = XSCALE1_COUNT0_EVT_MASK;
2430 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
2431 XSCALE1_COUNT0_INT_EN;
2433 case XSCALE_COUNTER1:
2434 mask = XSCALE1_COUNT1_EVT_MASK;
2435 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
2436 XSCALE1_COUNT1_INT_EN;
2439 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2443 spin_lock_irqsave(&pmu_lock, flags);
2444 val = xscale1pmu_read_pmnc();
2447 xscale1pmu_write_pmnc(val);
2448 spin_unlock_irqrestore(&pmu_lock, flags);
2452 xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
2454 unsigned long val, mask, evt, flags;
2457 case XSCALE_CYCLE_COUNTER:
2458 mask = XSCALE1_CCOUNT_INT_EN;
2461 case XSCALE_COUNTER0:
2462 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
2463 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
2465 case XSCALE_COUNTER1:
2466 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
2467 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
2470 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2474 spin_lock_irqsave(&pmu_lock, flags);
2475 val = xscale1pmu_read_pmnc();
2478 xscale1pmu_write_pmnc(val);
2479 spin_unlock_irqrestore(&pmu_lock, flags);
2483 xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
2484 struct hw_perf_event *event)
2486 if (XSCALE_PERFCTR_CCNT == event->config_base) {
2487 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
2490 return XSCALE_CYCLE_COUNTER;
2492 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
2493 return XSCALE_COUNTER1;
2496 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
2497 return XSCALE_COUNTER0;
2505 xscale1pmu_start(void)
2507 unsigned long flags, val;
2509 spin_lock_irqsave(&pmu_lock, flags);
2510 val = xscale1pmu_read_pmnc();
2511 val |= XSCALE_PMU_ENABLE;
2512 xscale1pmu_write_pmnc(val);
2513 spin_unlock_irqrestore(&pmu_lock, flags);
2517 xscale1pmu_stop(void)
2519 unsigned long flags, val;
2521 spin_lock_irqsave(&pmu_lock, flags);
2522 val = xscale1pmu_read_pmnc();
2523 val &= ~XSCALE_PMU_ENABLE;
2524 xscale1pmu_write_pmnc(val);
2525 spin_unlock_irqrestore(&pmu_lock, flags);
2529 xscale1pmu_read_counter(int counter)
2534 case XSCALE_CYCLE_COUNTER:
2535 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
2537 case XSCALE_COUNTER0:
2538 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
2540 case XSCALE_COUNTER1:
2541 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
2549 xscale1pmu_write_counter(int counter, u32 val)
2552 case XSCALE_CYCLE_COUNTER:
2553 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
2555 case XSCALE_COUNTER0:
2556 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
2558 case XSCALE_COUNTER1:
2559 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
2564 static const struct arm_pmu xscale1pmu = {
2565 .id = ARM_PERF_PMU_ID_XSCALE1,
2566 .handle_irq = xscale1pmu_handle_irq,
2567 .enable = xscale1pmu_enable_event,
2568 .disable = xscale1pmu_disable_event,
2569 .event_map = xscalepmu_event_map,
2570 .raw_event = xscalepmu_raw_event,
2571 .read_counter = xscale1pmu_read_counter,
2572 .write_counter = xscale1pmu_write_counter,
2573 .get_event_idx = xscale1pmu_get_event_idx,
2574 .start = xscale1pmu_start,
2575 .stop = xscale1pmu_stop,
2577 .max_period = (1LLU << 32) - 1,
2580 #define XSCALE2_OVERFLOWED_MASK 0x01f
2581 #define XSCALE2_CCOUNT_OVERFLOW 0x001
2582 #define XSCALE2_COUNT0_OVERFLOW 0x002
2583 #define XSCALE2_COUNT1_OVERFLOW 0x004
2584 #define XSCALE2_COUNT2_OVERFLOW 0x008
2585 #define XSCALE2_COUNT3_OVERFLOW 0x010
2586 #define XSCALE2_CCOUNT_INT_EN 0x001
2587 #define XSCALE2_COUNT0_INT_EN 0x002
2588 #define XSCALE2_COUNT1_INT_EN 0x004
2589 #define XSCALE2_COUNT2_INT_EN 0x008
2590 #define XSCALE2_COUNT3_INT_EN 0x010
2591 #define XSCALE2_COUNT0_EVT_SHFT 0
2592 #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
2593 #define XSCALE2_COUNT1_EVT_SHFT 8
2594 #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
2595 #define XSCALE2_COUNT2_EVT_SHFT 16
2596 #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
2597 #define XSCALE2_COUNT3_EVT_SHFT 24
2598 #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
2601 xscale2pmu_read_pmnc(void)
2604 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
2605 /* bits 1-2 and 4-23 are read-unpredictable */
2606 return val & 0xff000009;
2610 xscale2pmu_write_pmnc(u32 val)
2612 /* bits 4-23 are write-as-0, 24-31 are write ignored */
2614 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
2618 xscale2pmu_read_overflow_flags(void)
2621 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
2626 xscale2pmu_write_overflow_flags(u32 val)
2628 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
2632 xscale2pmu_read_event_select(void)
2635 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
2640 xscale2pmu_write_event_select(u32 val)
2642 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
2646 xscale2pmu_read_int_enable(void)
2649 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
2654 xscale2pmu_write_int_enable(u32 val)
2656 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
2660 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
2661 enum xscale_counters counter)
2666 case XSCALE_CYCLE_COUNTER:
2667 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
2669 case XSCALE_COUNTER0:
2670 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
2672 case XSCALE_COUNTER1:
2673 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
2675 case XSCALE_COUNTER2:
2676 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
2678 case XSCALE_COUNTER3:
2679 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
2682 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2689 xscale2pmu_handle_irq(int irq_num, void *dev)
2691 unsigned long pmnc, of_flags;
2692 struct perf_sample_data data;
2693 struct cpu_hw_events *cpuc;
2694 struct pt_regs *regs;
2697 /* Disable the PMU. */
2698 pmnc = xscale2pmu_read_pmnc();
2699 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2701 /* Check the overflow flag register. */
2702 of_flags = xscale2pmu_read_overflow_flags();
2703 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
2706 /* Clear the overflow bits. */
2707 xscale2pmu_write_overflow_flags(of_flags);
2709 regs = get_irq_regs();
2711 perf_sample_data_init(&data, 0);
2713 cpuc = &__get_cpu_var(cpu_hw_events);
2714 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2715 struct perf_event *event = cpuc->events[idx];
2716 struct hw_perf_event *hwc;
2718 if (!test_bit(idx, cpuc->active_mask))
2721 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
2725 armpmu_event_update(event, hwc, idx);
2726 data.period = event->hw.last_period;
2727 if (!armpmu_event_set_period(event, hwc, idx))
2730 if (perf_event_overflow(event, 0, &data, regs))
2731 armpmu->disable(hwc, idx);
2734 perf_event_do_pending();
2737 * Re-enable the PMU.
2739 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2740 xscale2pmu_write_pmnc(pmnc);
2746 xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
2748 unsigned long flags, ien, evtsel;
2750 ien = xscale2pmu_read_int_enable();
2751 evtsel = xscale2pmu_read_event_select();
2754 case XSCALE_CYCLE_COUNTER:
2755 ien |= XSCALE2_CCOUNT_INT_EN;
2757 case XSCALE_COUNTER0:
2758 ien |= XSCALE2_COUNT0_INT_EN;
2759 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2760 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
2762 case XSCALE_COUNTER1:
2763 ien |= XSCALE2_COUNT1_INT_EN;
2764 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2765 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
2767 case XSCALE_COUNTER2:
2768 ien |= XSCALE2_COUNT2_INT_EN;
2769 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2770 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
2772 case XSCALE_COUNTER3:
2773 ien |= XSCALE2_COUNT3_INT_EN;
2774 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2775 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
2778 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2782 spin_lock_irqsave(&pmu_lock, flags);
2783 xscale2pmu_write_event_select(evtsel);
2784 xscale2pmu_write_int_enable(ien);
2785 spin_unlock_irqrestore(&pmu_lock, flags);
2789 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
2791 unsigned long flags, ien, evtsel;
2793 ien = xscale2pmu_read_int_enable();
2794 evtsel = xscale2pmu_read_event_select();
2797 case XSCALE_CYCLE_COUNTER:
2798 ien &= ~XSCALE2_CCOUNT_INT_EN;
2800 case XSCALE_COUNTER0:
2801 ien &= ~XSCALE2_COUNT0_INT_EN;
2802 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2803 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
2805 case XSCALE_COUNTER1:
2806 ien &= ~XSCALE2_COUNT1_INT_EN;
2807 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2808 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
2810 case XSCALE_COUNTER2:
2811 ien &= ~XSCALE2_COUNT2_INT_EN;
2812 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2813 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
2815 case XSCALE_COUNTER3:
2816 ien &= ~XSCALE2_COUNT3_INT_EN;
2817 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2818 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
2821 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2825 spin_lock_irqsave(&pmu_lock, flags);
2826 xscale2pmu_write_event_select(evtsel);
2827 xscale2pmu_write_int_enable(ien);
2828 spin_unlock_irqrestore(&pmu_lock, flags);
2832 xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
2833 struct hw_perf_event *event)
2835 int idx = xscale1pmu_get_event_idx(cpuc, event);
2839 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
2840 idx = XSCALE_COUNTER3;
2841 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
2842 idx = XSCALE_COUNTER2;
2848 xscale2pmu_start(void)
2850 unsigned long flags, val;
2852 spin_lock_irqsave(&pmu_lock, flags);
2853 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
2854 val |= XSCALE_PMU_ENABLE;
2855 xscale2pmu_write_pmnc(val);
2856 spin_unlock_irqrestore(&pmu_lock, flags);
2860 xscale2pmu_stop(void)
2862 unsigned long flags, val;
2864 spin_lock_irqsave(&pmu_lock, flags);
2865 val = xscale2pmu_read_pmnc();
2866 val &= ~XSCALE_PMU_ENABLE;
2867 xscale2pmu_write_pmnc(val);
2868 spin_unlock_irqrestore(&pmu_lock, flags);
2872 xscale2pmu_read_counter(int counter)
2877 case XSCALE_CYCLE_COUNTER:
2878 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
2880 case XSCALE_COUNTER0:
2881 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
2883 case XSCALE_COUNTER1:
2884 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
2886 case XSCALE_COUNTER2:
2887 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
2889 case XSCALE_COUNTER3:
2890 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
2898 xscale2pmu_write_counter(int counter, u32 val)
2901 case XSCALE_CYCLE_COUNTER:
2902 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
2904 case XSCALE_COUNTER0:
2905 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
2907 case XSCALE_COUNTER1:
2908 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
2910 case XSCALE_COUNTER2:
2911 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
2913 case XSCALE_COUNTER3:
2914 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
2919 static const struct arm_pmu xscale2pmu = {
2920 .id = ARM_PERF_PMU_ID_XSCALE2,
2921 .handle_irq = xscale2pmu_handle_irq,
2922 .enable = xscale2pmu_enable_event,
2923 .disable = xscale2pmu_disable_event,
2924 .event_map = xscalepmu_event_map,
2925 .raw_event = xscalepmu_raw_event,
2926 .read_counter = xscale2pmu_read_counter,
2927 .write_counter = xscale2pmu_write_counter,
2928 .get_event_idx = xscale2pmu_get_event_idx,
2929 .start = xscale2pmu_start,
2930 .stop = xscale2pmu_stop,
2932 .max_period = (1LLU << 32) - 1,
2936 init_hw_perf_events(void)
2938 unsigned long cpuid = read_cpuid_id();
2939 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
2940 unsigned long part_number = (cpuid & 0xFFF0);
2943 if (0x41 == implementor) {
2944 switch (part_number) {
2945 case 0xB360: /* ARM1136 */
2946 case 0xB560: /* ARM1156 */
2947 case 0xB760: /* ARM1176 */
2949 memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
2950 sizeof(armv6_perf_cache_map));
2951 perf_max_events = armv6pmu.num_events;
2953 case 0xB020: /* ARM11mpcore */
2954 armpmu = &armv6mpcore_pmu;
2955 memcpy(armpmu_perf_cache_map,
2956 armv6mpcore_perf_cache_map,
2957 sizeof(armv6mpcore_perf_cache_map));
2958 perf_max_events = armv6mpcore_pmu.num_events;
2960 case 0xC080: /* Cortex-A8 */
2961 armv7pmu.id = ARM_PERF_PMU_ID_CA8;
2962 memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
2963 sizeof(armv7_a8_perf_cache_map));
2964 armv7pmu.event_map = armv7_a8_pmu_event_map;
2967 /* Reset PMNC and read the nb of CNTx counters
2969 armv7pmu.num_events = armv7_reset_read_pmnc();
2970 perf_max_events = armv7pmu.num_events;
2972 case 0xC090: /* Cortex-A9 */
2973 armv7pmu.id = ARM_PERF_PMU_ID_CA9;
2974 memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
2975 sizeof(armv7_a9_perf_cache_map));
2976 armv7pmu.event_map = armv7_a9_pmu_event_map;
2979 /* Reset PMNC and read the nb of CNTx counters
2981 armv7pmu.num_events = armv7_reset_read_pmnc();
2982 perf_max_events = armv7pmu.num_events;
2985 /* Intel CPUs [xscale]. */
2986 } else if (0x69 == implementor) {
2987 part_number = (cpuid >> 13) & 0x7;
2988 switch (part_number) {
2990 armpmu = &xscale1pmu;
2991 memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2992 sizeof(xscale_perf_cache_map));
2993 perf_max_events = xscale1pmu.num_events;
2996 armpmu = &xscale2pmu;
2997 memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
2998 sizeof(xscale_perf_cache_map));
2999 perf_max_events = xscale2pmu.num_events;
3005 pr_info("enabled with %s PMU driver, %d counters available\n",
3006 arm_pmu_names[armpmu->id], armpmu->num_events);
3008 pr_info("no hardware support available\n");
3009 perf_max_events = -1;
3012 perf_pmu_register(&pmu);
3016 arch_initcall(init_hw_perf_events);
3019 * Callchain handling code.
3023 * The registers we're interested in are at the end of the variable
3024 * length saved register structure. The fp points at the end of this
3025 * structure so the address of this struct is:
3026 * (struct frame_tail *)(xxx->fp)-1
3028 * This code has been adapted from the ARM OProfile support.
3031 struct frame_tail *fp;
3034 } __attribute__((packed));
3037 * Get the return address for a single stackframe and return a pointer to the
3040 static struct frame_tail *
3041 user_backtrace(struct frame_tail *tail,
3042 struct perf_callchain_entry *entry)
3044 struct frame_tail buftail;
3046 /* Also check accessibility of one struct frame_tail beyond */
3047 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
3049 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
3052 perf_callchain_store(entry, buftail.lr);
3055 * Frame pointers should strictly progress back up the stack
3056 * (towards higher addresses).
3058 if (tail >= buftail.fp)
3061 return buftail.fp - 1;
3065 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
3067 struct frame_tail *tail;
3070 tail = (struct frame_tail *)regs->ARM_fp - 1;
3072 while (tail && !((unsigned long)tail & 0x3))
3073 tail = user_backtrace(tail, entry);
3077 * Gets called by walk_stackframe() for every stackframe. This will be called
3078 * whist unwinding the stackframe and is like a subroutine return so we use
3082 callchain_trace(struct stackframe *fr,
3085 struct perf_callchain_entry *entry = data;
3086 perf_callchain_store(entry, fr->pc);
3091 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
3093 struct stackframe fr;
3095 fr.fp = regs->ARM_fp;
3096 fr.sp = regs->ARM_sp;
3097 fr.lr = regs->ARM_lr;
3098 fr.pc = regs->ARM_pc;
3099 walk_stackframe(&fr, callchain_trace, entry);