4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
10 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/perf_event.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/uaccess.h>
23 #include <asm/cputype.h>
25 #include <asm/irq_regs.h>
27 #include <asm/stacktrace.h>
29 static struct platform_device *pmu_device;
32 * Hardware lock to serialize accesses to PMU registers. Needed for the
33 * read/modify/write sequences.
35 static DEFINE_RAW_SPINLOCK(pmu_lock);
38 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
39 * another platform that supports more, we need to increase this to be the
40 * largest of all platforms.
42 * ARMv7 supports up to 32 events:
43 * cycle counter CCNT + 31 events counters CNT0..30.
44 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
46 #define ARMPMU_MAX_HWEVENTS 33
48 /* The events for a given CPU. */
49 struct cpu_hw_events {
51 * The events that are active on the CPU for the given index. Index 0
54 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
57 * A 1 bit for an index indicates that the counter is being used for
58 * an event. A 0 means that the counter can be used.
60 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
63 * A 1 bit for an index indicates that the counter is actively being
66 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
68 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
71 enum arm_perf_pmu_ids id;
73 irqreturn_t (*handle_irq)(int irq_num, void *dev);
74 void (*enable)(struct hw_perf_event *evt, int idx);
75 void (*disable)(struct hw_perf_event *evt, int idx);
76 int (*get_event_idx)(struct cpu_hw_events *cpuc,
77 struct hw_perf_event *hwc);
78 u32 (*read_counter)(int idx);
79 void (*write_counter)(int idx, u32 val);
82 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
83 [PERF_COUNT_HW_CACHE_OP_MAX]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX];
85 const unsigned (*event_map)[PERF_COUNT_HW_MAX];
91 /* Set at runtime when we know what CPU type we are. */
92 static const struct arm_pmu *armpmu;
95 armpmu_get_pmu_id(void)
104 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
107 armpmu_get_max_events(void)
112 max_events = armpmu->num_events;
116 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
118 int perf_num_counters(void)
120 return armpmu_get_max_events();
122 EXPORT_SYMBOL_GPL(perf_num_counters);
124 #define HW_OP_UNSUPPORTED 0xFFFF
127 PERF_COUNT_HW_CACHE_##_x
129 #define CACHE_OP_UNSUPPORTED 0xFFFF
132 armpmu_map_cache_event(u64 config)
134 unsigned int cache_type, cache_op, cache_result, ret;
136 cache_type = (config >> 0) & 0xff;
137 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
140 cache_op = (config >> 8) & 0xff;
141 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
144 cache_result = (config >> 16) & 0xff;
145 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
148 ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
150 if (ret == CACHE_OP_UNSUPPORTED)
157 armpmu_map_event(u64 config)
159 int mapping = (*armpmu->event_map)[config];
160 return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
164 armpmu_map_raw_event(u64 config)
166 return (int)(config & armpmu->raw_event_mask);
170 armpmu_event_set_period(struct perf_event *event,
171 struct hw_perf_event *hwc,
174 s64 left = local64_read(&hwc->period_left);
175 s64 period = hwc->sample_period;
178 if (unlikely(left <= -period)) {
180 local64_set(&hwc->period_left, left);
181 hwc->last_period = period;
185 if (unlikely(left <= 0)) {
187 local64_set(&hwc->period_left, left);
188 hwc->last_period = period;
192 if (left > (s64)armpmu->max_period)
193 left = armpmu->max_period;
195 local64_set(&hwc->prev_count, (u64)-left);
197 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
199 perf_event_update_userpage(event);
205 armpmu_event_update(struct perf_event *event,
206 struct hw_perf_event *hwc,
210 s64 prev_raw_count, new_raw_count;
214 prev_raw_count = local64_read(&hwc->prev_count);
215 new_raw_count = armpmu->read_counter(idx);
217 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
218 new_raw_count) != prev_raw_count)
221 delta = (new_raw_count << shift) - (prev_raw_count << shift);
224 local64_add(delta, &event->count);
225 local64_sub(delta, &hwc->period_left);
227 return new_raw_count;
231 armpmu_read(struct perf_event *event)
233 struct hw_perf_event *hwc = &event->hw;
235 /* Don't read disabled counters! */
239 armpmu_event_update(event, hwc, hwc->idx);
243 armpmu_stop(struct perf_event *event, int flags)
245 struct hw_perf_event *hwc = &event->hw;
251 * ARM pmu always has to update the counter, so ignore
252 * PERF_EF_UPDATE, see comments in armpmu_start().
254 if (!(hwc->state & PERF_HES_STOPPED)) {
255 armpmu->disable(hwc, hwc->idx);
256 barrier(); /* why? */
257 armpmu_event_update(event, hwc, hwc->idx);
258 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
263 armpmu_start(struct perf_event *event, int flags)
265 struct hw_perf_event *hwc = &event->hw;
271 * ARM pmu always has to reprogram the period, so ignore
272 * PERF_EF_RELOAD, see the comment below.
274 if (flags & PERF_EF_RELOAD)
275 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
279 * Set the period again. Some counters can't be stopped, so when we
280 * were stopped we simply disabled the IRQ source and the counter
281 * may have been left counting. If we don't do this step then we may
282 * get an interrupt too soon or *way* too late if the overflow has
283 * happened since disabling.
285 armpmu_event_set_period(event, hwc, hwc->idx);
286 armpmu->enable(hwc, hwc->idx);
290 armpmu_del(struct perf_event *event, int flags)
292 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
293 struct hw_perf_event *hwc = &event->hw;
298 clear_bit(idx, cpuc->active_mask);
299 armpmu_stop(event, PERF_EF_UPDATE);
300 cpuc->events[idx] = NULL;
301 clear_bit(idx, cpuc->used_mask);
303 perf_event_update_userpage(event);
307 armpmu_add(struct perf_event *event, int flags)
309 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
310 struct hw_perf_event *hwc = &event->hw;
314 perf_pmu_disable(event->pmu);
316 /* If we don't have a space for the counter then finish early. */
317 idx = armpmu->get_event_idx(cpuc, hwc);
324 * If there is an event in the counter we are going to use then make
325 * sure it is disabled.
328 armpmu->disable(hwc, idx);
329 cpuc->events[idx] = event;
330 set_bit(idx, cpuc->active_mask);
332 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
333 if (flags & PERF_EF_START)
334 armpmu_start(event, PERF_EF_RELOAD);
336 /* Propagate our changes to the userspace mapping. */
337 perf_event_update_userpage(event);
340 perf_pmu_enable(event->pmu);
344 static struct pmu pmu;
347 validate_event(struct cpu_hw_events *cpuc,
348 struct perf_event *event)
350 struct hw_perf_event fake_event = event->hw;
352 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
355 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
359 validate_group(struct perf_event *event)
361 struct perf_event *sibling, *leader = event->group_leader;
362 struct cpu_hw_events fake_pmu;
364 memset(&fake_pmu, 0, sizeof(fake_pmu));
366 if (!validate_event(&fake_pmu, leader))
369 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
370 if (!validate_event(&fake_pmu, sibling))
374 if (!validate_event(&fake_pmu, event))
381 armpmu_reserve_hardware(void)
383 int i, err = -ENODEV, irq;
385 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
386 if (IS_ERR(pmu_device)) {
387 pr_warning("unable to reserve pmu\n");
388 return PTR_ERR(pmu_device);
391 init_pmu(ARM_PMU_DEVICE_CPU);
393 if (pmu_device->num_resources < 1) {
394 pr_err("no irqs for PMUs defined\n");
398 for (i = 0; i < pmu_device->num_resources; ++i) {
399 irq = platform_get_irq(pmu_device, i);
403 err = request_irq(irq, armpmu->handle_irq,
404 IRQF_DISABLED | IRQF_NOBALANCING,
407 pr_warning("unable to request IRQ%d for ARM perf "
414 for (i = i - 1; i >= 0; --i) {
415 irq = platform_get_irq(pmu_device, i);
419 release_pmu(pmu_device);
427 armpmu_release_hardware(void)
431 for (i = pmu_device->num_resources - 1; i >= 0; --i) {
432 irq = platform_get_irq(pmu_device, i);
438 release_pmu(pmu_device);
442 static atomic_t active_events = ATOMIC_INIT(0);
443 static DEFINE_MUTEX(pmu_reserve_mutex);
446 hw_perf_event_destroy(struct perf_event *event)
448 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
449 armpmu_release_hardware();
450 mutex_unlock(&pmu_reserve_mutex);
455 __hw_perf_event_init(struct perf_event *event)
457 struct hw_perf_event *hwc = &event->hw;
460 /* Decode the generic type into an ARM event identifier. */
461 if (PERF_TYPE_HARDWARE == event->attr.type) {
462 mapping = armpmu_map_event(event->attr.config);
463 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
464 mapping = armpmu_map_cache_event(event->attr.config);
465 } else if (PERF_TYPE_RAW == event->attr.type) {
466 mapping = armpmu_map_raw_event(event->attr.config);
468 pr_debug("event type %x not supported\n", event->attr.type);
473 pr_debug("event %x:%llx not supported\n", event->attr.type,
479 * Check whether we need to exclude the counter from certain modes.
480 * The ARM performance counters are on all of the time so if someone
481 * has asked us for some excludes then we have to fail.
483 if (event->attr.exclude_kernel || event->attr.exclude_user ||
484 event->attr.exclude_hv || event->attr.exclude_idle) {
485 pr_debug("ARM performance counters do not support "
491 * We don't assign an index until we actually place the event onto
492 * hardware. Use -1 to signify that we haven't decided where to put it
493 * yet. For SMP systems, each core has it's own PMU so we can't do any
494 * clever allocation or constraints checking at this point.
499 * Store the event encoding into the config_base field. config and
500 * event_base are unused as the only 2 things we need to know are
501 * the event mapping and the counter to use. The counter to use is
502 * also the indx and the config_base is the event type.
504 hwc->config_base = (unsigned long)mapping;
508 if (!hwc->sample_period) {
509 hwc->sample_period = armpmu->max_period;
510 hwc->last_period = hwc->sample_period;
511 local64_set(&hwc->period_left, hwc->sample_period);
515 if (event->group_leader != event) {
516 err = validate_group(event);
524 static int armpmu_event_init(struct perf_event *event)
528 switch (event->attr.type) {
530 case PERF_TYPE_HARDWARE:
531 case PERF_TYPE_HW_CACHE:
541 event->destroy = hw_perf_event_destroy;
543 if (!atomic_inc_not_zero(&active_events)) {
544 if (atomic_read(&active_events) > armpmu->num_events) {
545 atomic_dec(&active_events);
549 mutex_lock(&pmu_reserve_mutex);
550 if (atomic_read(&active_events) == 0) {
551 err = armpmu_reserve_hardware();
555 atomic_inc(&active_events);
556 mutex_unlock(&pmu_reserve_mutex);
562 err = __hw_perf_event_init(event);
564 hw_perf_event_destroy(event);
569 static void armpmu_enable(struct pmu *pmu)
571 /* Enable all of the perf events on hardware. */
573 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
578 for (idx = 0; idx <= armpmu->num_events; ++idx) {
579 struct perf_event *event = cpuc->events[idx];
584 armpmu->enable(&event->hw, idx);
590 static void armpmu_disable(struct pmu *pmu)
596 static struct pmu pmu = {
597 .pmu_enable = armpmu_enable,
598 .pmu_disable = armpmu_disable,
599 .event_init = armpmu_event_init,
602 .start = armpmu_start,
607 /* Include the PMU-specific implementations. */
608 #include "perf_event_xscale.c"
609 #include "perf_event_v6.c"
610 #include "perf_event_v7.c"
613 init_hw_perf_events(void)
615 unsigned long cpuid = read_cpuid_id();
616 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
617 unsigned long part_number = (cpuid & 0xFFF0);
620 if (0x41 == implementor) {
621 switch (part_number) {
622 case 0xB360: /* ARM1136 */
623 case 0xB560: /* ARM1156 */
624 case 0xB760: /* ARM1176 */
625 armpmu = armv6pmu_init();
627 case 0xB020: /* ARM11mpcore */
628 armpmu = armv6mpcore_pmu_init();
630 case 0xC080: /* Cortex-A8 */
631 armpmu = armv7_a8_pmu_init();
633 case 0xC090: /* Cortex-A9 */
634 armpmu = armv7_a9_pmu_init();
637 /* Intel CPUs [xscale]. */
638 } else if (0x69 == implementor) {
639 part_number = (cpuid >> 13) & 0x7;
640 switch (part_number) {
642 armpmu = xscale1pmu_init();
645 armpmu = xscale2pmu_init();
651 pr_info("enabled with %s PMU driver, %d counters available\n",
652 armpmu->name, armpmu->num_events);
654 pr_info("no hardware support available\n");
657 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
661 early_initcall(init_hw_perf_events);
664 * Callchain handling code.
668 * The registers we're interested in are at the end of the variable
669 * length saved register structure. The fp points at the end of this
670 * structure so the address of this struct is:
671 * (struct frame_tail *)(xxx->fp)-1
673 * This code has been adapted from the ARM OProfile support.
676 struct frame_tail __user *fp;
679 } __attribute__((packed));
682 * Get the return address for a single stackframe and return a pointer to the
685 static struct frame_tail __user *
686 user_backtrace(struct frame_tail __user *tail,
687 struct perf_callchain_entry *entry)
689 struct frame_tail buftail;
691 /* Also check accessibility of one struct frame_tail beyond */
692 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
694 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
697 perf_callchain_store(entry, buftail.lr);
700 * Frame pointers should strictly progress back up the stack
701 * (towards higher addresses).
703 if (tail >= buftail.fp)
706 return buftail.fp - 1;
710 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
712 struct frame_tail __user *tail;
715 tail = (struct frame_tail __user *)regs->ARM_fp - 1;
717 while (tail && !((unsigned long)tail & 0x3))
718 tail = user_backtrace(tail, entry);
722 * Gets called by walk_stackframe() for every stackframe. This will be called
723 * whist unwinding the stackframe and is like a subroutine return so we use
727 callchain_trace(struct stackframe *fr,
730 struct perf_callchain_entry *entry = data;
731 perf_callchain_store(entry, fr->pc);
736 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
738 struct stackframe fr;
740 fr.fp = regs->ARM_fp;
741 fr.sp = regs->ARM_sp;
742 fr.lr = regs->ARM_lr;
743 fr.pc = regs->ARM_pc;
744 walk_stackframe(&fr, callchain_trace, entry);