2 * ARMv5 [xscale] Performance counter handling code.
4 * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
6 * Based on the previous xscale OProfile code.
8 * There are two variants of the xscale PMU that we support:
9 * - xscale1pmu: 2 event counters and a cycle counter
10 * - xscale2pmu: 4 event counters and a cycle counter
11 * The two variants share event definitions, but have different
15 #ifdef CONFIG_CPU_XSCALE
16 enum xscale_perf_types {
17 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
18 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
19 XSCALE_PERFCTR_DATA_STALL = 0x02,
20 XSCALE_PERFCTR_ITLB_MISS = 0x03,
21 XSCALE_PERFCTR_DTLB_MISS = 0x04,
22 XSCALE_PERFCTR_BRANCH = 0x05,
23 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
24 XSCALE_PERFCTR_INSTRUCTION = 0x07,
25 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
26 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
27 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
28 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
29 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
30 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
31 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
32 XSCALE_PERFCTR_BCU_FULL = 0x11,
33 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
34 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
35 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
36 XSCALE_PERFCTR_RMW = 0x16,
37 /* XSCALE_PERFCTR_CCNT is not hardware defined */
38 XSCALE_PERFCTR_CCNT = 0xFE,
39 XSCALE_PERFCTR_UNUSED = 0xFF,
42 enum xscale_counters {
43 XSCALE_CYCLE_COUNTER = 1,
50 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
51 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
52 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
53 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
54 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
55 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
56 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
57 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
60 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
61 [PERF_COUNT_HW_CACHE_OP_MAX]
62 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
65 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
66 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
69 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
70 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
73 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
74 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
79 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
80 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
83 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
84 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
87 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
88 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
93 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
94 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
97 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
98 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
101 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
102 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
107 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
108 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
111 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
112 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
115 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
116 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
121 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
122 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
125 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
126 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
129 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
130 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
135 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
136 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
139 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
140 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
143 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
144 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
149 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
150 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
153 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
154 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
157 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
158 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
163 #define XSCALE_PMU_ENABLE 0x001
164 #define XSCALE_PMN_RESET 0x002
165 #define XSCALE_CCNT_RESET 0x004
166 #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
167 #define XSCALE_PMU_CNT64 0x008
169 #define XSCALE1_OVERFLOWED_MASK 0x700
170 #define XSCALE1_CCOUNT_OVERFLOW 0x400
171 #define XSCALE1_COUNT0_OVERFLOW 0x100
172 #define XSCALE1_COUNT1_OVERFLOW 0x200
173 #define XSCALE1_CCOUNT_INT_EN 0x040
174 #define XSCALE1_COUNT0_INT_EN 0x010
175 #define XSCALE1_COUNT1_INT_EN 0x020
176 #define XSCALE1_COUNT0_EVT_SHFT 12
177 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
178 #define XSCALE1_COUNT1_EVT_SHFT 20
179 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
182 xscale1pmu_read_pmnc(void)
185 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
190 xscale1pmu_write_pmnc(u32 val)
192 /* upper 4bits and 7, 11 are write-as-0 */
194 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
198 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
199 enum xscale_counters counter)
204 case XSCALE_CYCLE_COUNTER:
205 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
207 case XSCALE_COUNTER0:
208 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
210 case XSCALE_COUNTER1:
211 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
214 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
221 xscale1pmu_handle_irq(int irq_num, void *dev)
224 struct perf_sample_data data;
225 struct cpu_hw_events *cpuc;
226 struct pt_regs *regs;
230 * NOTE: there's an A stepping erratum that states if an overflow
231 * bit already exists and another occurs, the previous
232 * Overflow bit gets cleared. There's no workaround.
233 * Fixed in B stepping or later.
235 pmnc = xscale1pmu_read_pmnc();
238 * Write the value back to clear the overflow flags. Overflow
239 * flags remain in pmnc for use below. We also disable the PMU
240 * while we process the interrupt.
242 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
244 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
247 regs = get_irq_regs();
249 perf_sample_data_init(&data, 0);
251 cpuc = &__get_cpu_var(cpu_hw_events);
252 for (idx = 0; idx <= armpmu->num_events; ++idx) {
253 struct perf_event *event = cpuc->events[idx];
254 struct hw_perf_event *hwc;
256 if (!test_bit(idx, cpuc->active_mask))
259 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
263 armpmu_event_update(event, hwc, idx, 1);
264 data.period = event->hw.last_period;
265 if (!armpmu_event_set_period(event, hwc, idx))
268 if (perf_event_overflow(event, &data, regs))
269 armpmu->disable(hwc, idx);
277 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
278 xscale1pmu_write_pmnc(pmnc);
284 xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
286 unsigned long val, mask, evt, flags;
289 case XSCALE_CYCLE_COUNTER:
291 evt = XSCALE1_CCOUNT_INT_EN;
293 case XSCALE_COUNTER0:
294 mask = XSCALE1_COUNT0_EVT_MASK;
295 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
296 XSCALE1_COUNT0_INT_EN;
298 case XSCALE_COUNTER1:
299 mask = XSCALE1_COUNT1_EVT_MASK;
300 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
301 XSCALE1_COUNT1_INT_EN;
304 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
308 raw_spin_lock_irqsave(&pmu_lock, flags);
309 val = xscale1pmu_read_pmnc();
312 xscale1pmu_write_pmnc(val);
313 raw_spin_unlock_irqrestore(&pmu_lock, flags);
317 xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
319 unsigned long val, mask, evt, flags;
322 case XSCALE_CYCLE_COUNTER:
323 mask = XSCALE1_CCOUNT_INT_EN;
326 case XSCALE_COUNTER0:
327 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
328 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
330 case XSCALE_COUNTER1:
331 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
332 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
335 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
339 raw_spin_lock_irqsave(&pmu_lock, flags);
340 val = xscale1pmu_read_pmnc();
343 xscale1pmu_write_pmnc(val);
344 raw_spin_unlock_irqrestore(&pmu_lock, flags);
348 xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
349 struct hw_perf_event *event)
351 if (XSCALE_PERFCTR_CCNT == event->config_base) {
352 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
355 return XSCALE_CYCLE_COUNTER;
357 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
358 return XSCALE_COUNTER1;
360 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
361 return XSCALE_COUNTER0;
368 xscale1pmu_start(void)
370 unsigned long flags, val;
372 raw_spin_lock_irqsave(&pmu_lock, flags);
373 val = xscale1pmu_read_pmnc();
374 val |= XSCALE_PMU_ENABLE;
375 xscale1pmu_write_pmnc(val);
376 raw_spin_unlock_irqrestore(&pmu_lock, flags);
380 xscale1pmu_stop(void)
382 unsigned long flags, val;
384 raw_spin_lock_irqsave(&pmu_lock, flags);
385 val = xscale1pmu_read_pmnc();
386 val &= ~XSCALE_PMU_ENABLE;
387 xscale1pmu_write_pmnc(val);
388 raw_spin_unlock_irqrestore(&pmu_lock, flags);
392 xscale1pmu_read_counter(int counter)
397 case XSCALE_CYCLE_COUNTER:
398 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
400 case XSCALE_COUNTER0:
401 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
403 case XSCALE_COUNTER1:
404 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
412 xscale1pmu_write_counter(int counter, u32 val)
415 case XSCALE_CYCLE_COUNTER:
416 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
418 case XSCALE_COUNTER0:
419 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
421 case XSCALE_COUNTER1:
422 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
427 static const struct arm_pmu xscale1pmu = {
428 .id = ARM_PERF_PMU_ID_XSCALE1,
430 .handle_irq = xscale1pmu_handle_irq,
431 .enable = xscale1pmu_enable_event,
432 .disable = xscale1pmu_disable_event,
433 .read_counter = xscale1pmu_read_counter,
434 .write_counter = xscale1pmu_write_counter,
435 .get_event_idx = xscale1pmu_get_event_idx,
436 .start = xscale1pmu_start,
437 .stop = xscale1pmu_stop,
438 .cache_map = &xscale_perf_cache_map,
439 .event_map = &xscale_perf_map,
440 .raw_event_mask = 0xFF,
442 .max_period = (1LLU << 32) - 1,
445 static const struct arm_pmu *__init xscale1pmu_init(void)
450 #define XSCALE2_OVERFLOWED_MASK 0x01f
451 #define XSCALE2_CCOUNT_OVERFLOW 0x001
452 #define XSCALE2_COUNT0_OVERFLOW 0x002
453 #define XSCALE2_COUNT1_OVERFLOW 0x004
454 #define XSCALE2_COUNT2_OVERFLOW 0x008
455 #define XSCALE2_COUNT3_OVERFLOW 0x010
456 #define XSCALE2_CCOUNT_INT_EN 0x001
457 #define XSCALE2_COUNT0_INT_EN 0x002
458 #define XSCALE2_COUNT1_INT_EN 0x004
459 #define XSCALE2_COUNT2_INT_EN 0x008
460 #define XSCALE2_COUNT3_INT_EN 0x010
461 #define XSCALE2_COUNT0_EVT_SHFT 0
462 #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
463 #define XSCALE2_COUNT1_EVT_SHFT 8
464 #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
465 #define XSCALE2_COUNT2_EVT_SHFT 16
466 #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
467 #define XSCALE2_COUNT3_EVT_SHFT 24
468 #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
471 xscale2pmu_read_pmnc(void)
474 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
475 /* bits 1-2 and 4-23 are read-unpredictable */
476 return val & 0xff000009;
480 xscale2pmu_write_pmnc(u32 val)
482 /* bits 4-23 are write-as-0, 24-31 are write ignored */
484 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
488 xscale2pmu_read_overflow_flags(void)
491 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
496 xscale2pmu_write_overflow_flags(u32 val)
498 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
502 xscale2pmu_read_event_select(void)
505 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
510 xscale2pmu_write_event_select(u32 val)
512 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
516 xscale2pmu_read_int_enable(void)
519 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
524 xscale2pmu_write_int_enable(u32 val)
526 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
530 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
531 enum xscale_counters counter)
536 case XSCALE_CYCLE_COUNTER:
537 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
539 case XSCALE_COUNTER0:
540 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
542 case XSCALE_COUNTER1:
543 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
545 case XSCALE_COUNTER2:
546 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
548 case XSCALE_COUNTER3:
549 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
552 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
559 xscale2pmu_handle_irq(int irq_num, void *dev)
561 unsigned long pmnc, of_flags;
562 struct perf_sample_data data;
563 struct cpu_hw_events *cpuc;
564 struct pt_regs *regs;
567 /* Disable the PMU. */
568 pmnc = xscale2pmu_read_pmnc();
569 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
571 /* Check the overflow flag register. */
572 of_flags = xscale2pmu_read_overflow_flags();
573 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
576 /* Clear the overflow bits. */
577 xscale2pmu_write_overflow_flags(of_flags);
579 regs = get_irq_regs();
581 perf_sample_data_init(&data, 0);
583 cpuc = &__get_cpu_var(cpu_hw_events);
584 for (idx = 0; idx <= armpmu->num_events; ++idx) {
585 struct perf_event *event = cpuc->events[idx];
586 struct hw_perf_event *hwc;
588 if (!test_bit(idx, cpuc->active_mask))
591 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
595 armpmu_event_update(event, hwc, idx, 1);
596 data.period = event->hw.last_period;
597 if (!armpmu_event_set_period(event, hwc, idx))
600 if (perf_event_overflow(event, &data, regs))
601 armpmu->disable(hwc, idx);
609 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
610 xscale2pmu_write_pmnc(pmnc);
616 xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
618 unsigned long flags, ien, evtsel;
620 ien = xscale2pmu_read_int_enable();
621 evtsel = xscale2pmu_read_event_select();
624 case XSCALE_CYCLE_COUNTER:
625 ien |= XSCALE2_CCOUNT_INT_EN;
627 case XSCALE_COUNTER0:
628 ien |= XSCALE2_COUNT0_INT_EN;
629 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
630 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
632 case XSCALE_COUNTER1:
633 ien |= XSCALE2_COUNT1_INT_EN;
634 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
635 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
637 case XSCALE_COUNTER2:
638 ien |= XSCALE2_COUNT2_INT_EN;
639 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
640 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
642 case XSCALE_COUNTER3:
643 ien |= XSCALE2_COUNT3_INT_EN;
644 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
645 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
648 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
652 raw_spin_lock_irqsave(&pmu_lock, flags);
653 xscale2pmu_write_event_select(evtsel);
654 xscale2pmu_write_int_enable(ien);
655 raw_spin_unlock_irqrestore(&pmu_lock, flags);
659 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
661 unsigned long flags, ien, evtsel;
663 ien = xscale2pmu_read_int_enable();
664 evtsel = xscale2pmu_read_event_select();
667 case XSCALE_CYCLE_COUNTER:
668 ien &= ~XSCALE2_CCOUNT_INT_EN;
670 case XSCALE_COUNTER0:
671 ien &= ~XSCALE2_COUNT0_INT_EN;
672 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
673 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
675 case XSCALE_COUNTER1:
676 ien &= ~XSCALE2_COUNT1_INT_EN;
677 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
678 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
680 case XSCALE_COUNTER2:
681 ien &= ~XSCALE2_COUNT2_INT_EN;
682 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
683 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
685 case XSCALE_COUNTER3:
686 ien &= ~XSCALE2_COUNT3_INT_EN;
687 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
688 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
691 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
695 raw_spin_lock_irqsave(&pmu_lock, flags);
696 xscale2pmu_write_event_select(evtsel);
697 xscale2pmu_write_int_enable(ien);
698 raw_spin_unlock_irqrestore(&pmu_lock, flags);
702 xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
703 struct hw_perf_event *event)
705 int idx = xscale1pmu_get_event_idx(cpuc, event);
709 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
710 idx = XSCALE_COUNTER3;
711 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
712 idx = XSCALE_COUNTER2;
718 xscale2pmu_start(void)
720 unsigned long flags, val;
722 raw_spin_lock_irqsave(&pmu_lock, flags);
723 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
724 val |= XSCALE_PMU_ENABLE;
725 xscale2pmu_write_pmnc(val);
726 raw_spin_unlock_irqrestore(&pmu_lock, flags);
730 xscale2pmu_stop(void)
732 unsigned long flags, val;
734 raw_spin_lock_irqsave(&pmu_lock, flags);
735 val = xscale2pmu_read_pmnc();
736 val &= ~XSCALE_PMU_ENABLE;
737 xscale2pmu_write_pmnc(val);
738 raw_spin_unlock_irqrestore(&pmu_lock, flags);
742 xscale2pmu_read_counter(int counter)
747 case XSCALE_CYCLE_COUNTER:
748 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
750 case XSCALE_COUNTER0:
751 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
753 case XSCALE_COUNTER1:
754 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
756 case XSCALE_COUNTER2:
757 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
759 case XSCALE_COUNTER3:
760 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
768 xscale2pmu_write_counter(int counter, u32 val)
771 case XSCALE_CYCLE_COUNTER:
772 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
774 case XSCALE_COUNTER0:
775 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
777 case XSCALE_COUNTER1:
778 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
780 case XSCALE_COUNTER2:
781 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
783 case XSCALE_COUNTER3:
784 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
789 static const struct arm_pmu xscale2pmu = {
790 .id = ARM_PERF_PMU_ID_XSCALE2,
792 .handle_irq = xscale2pmu_handle_irq,
793 .enable = xscale2pmu_enable_event,
794 .disable = xscale2pmu_disable_event,
795 .read_counter = xscale2pmu_read_counter,
796 .write_counter = xscale2pmu_write_counter,
797 .get_event_idx = xscale2pmu_get_event_idx,
798 .start = xscale2pmu_start,
799 .stop = xscale2pmu_stop,
800 .cache_map = &xscale_perf_cache_map,
801 .event_map = &xscale_perf_map,
802 .raw_event_mask = 0xFF,
804 .max_period = (1LLU << 32) - 1,
807 static const struct arm_pmu *__init xscale2pmu_init(void)
812 static const struct arm_pmu *__init xscale1pmu_init(void)
817 static const struct arm_pmu *__init xscale2pmu_init(void)
821 #endif /* CONFIG_CPU_XSCALE */